================================================================================
Multi-Core Intel(R) Xeon(R) Processor-Based Server PLD Development
================================================================================
INTEL Enterprise Products and Services Division
Intel Corporation
2111 N.E. 25th Avenue, Hillsboro, OR 97124 USA

================================================================================
DATE    : February 18, 2020
TO      : Multi-Core Intel(R) Xeon(R) Processor-Based Server Platform customers
SUBJECT : Whitley Main PLD for Whitley Platform based, Common Core code included

================================================================================
                           LEGAL INFORMATION
================================================================================
Information in this document is provided in connection with Intel Products
and for the purpose of supporting Intel developed server boards and systems.
No license, express or implied, by estoppel or otherwise, to any intellectual 
property rights is granted by this document. Except as provided in Intel's 
Terms and Conditions of Sale for such products, Intel assumes no liability 
whatsoever, and Intel disclaims any express or implied warranty, relating to 
sale and/or use of Intel products including liability or warranties relating 
to fitness for a particular purpose, merchantability, or infringement of any 
patent, copyright or other intellectual property right. Intel Corporation 
may have patents or pending patent applications, trademarks, copyrights, or
other intellectual property rights that relate to the presented subject matter.
The furnishing of documents and other materials and information does not 
provide any license, express or implied, by estoppel or otherwise, to any such
patents, trademarks, copyrights, or other intellectual property rights.  
Intel products are not intended for use in medical, life saving, or life 
sustaining applications. Intel may make changes to specifications and product
descriptions at any time, without notice.

Intel is a registered trademark of Intel Corporation. 

*Other names and brands are the property of their respective owners.

Copyright (C) 2020  Intel Corporation.


================================================================================
							INSTALLATION NOTES
================================================================================
ATTENTION: 

Please use the TOPs intructions (doc#:615382) to correctly program the CPLD/FPGA's.
Use FPGA JTAG Cable (Altera Blaster II) to burn the .pof image into the FPGA chip.

================================================================================
							KNOWN ISSUES/WORKAROUND
================================================================================

- Images 1.X only for fab1, 2.X only for fab2 due to pin incompatibility


================================================================================
							UPDATES
================================================================================

==========
[Main-PFR]
==========

- Fix to enter Package C6 state in 4 Socket configuration.  
  The Modular CPLD is now keeping PM_FAST_WAKE_N low at all times when in 4S/8S 
  configuration.  

- Main CPLD masks ADR_TRIGGER from Modular CPLD before PLTRST# to fix boot With LBG-R.    

- Fix SMB routing thru Main CPLD to update VRD (Voltage Regulators) through the onboard SMB header.

- Feature add: Added BIOS ID change for 4S/8S UPI topology detection for UPI TX EQ settings at early boot.  
  
- Incorporated code based on 2.3 main to fix Non Legacy UPI training due to PCH_PWROK being high.

- Tested with PFR version 393.6 revision. Main CPLD is still reflects the 2.5 7-segment display.  

================
[Debug Modular]
================
Modular 0.C - Compatible with main up to 2.2

Modular 0.F - Compatible with 2.5 and forward

Modular 1.00 - Compatible with 2.5 and forward
	- Solved shutdown issue for all systems (2s, 4s, 8s) provoqued by SYS_PWROK handling while implementing architecture work around
	- Removed random glitches on Fast Wake, delay enhancement not included.
	- Masked PWR_Debug signal using XDP present.
	
Modular 1.01 - Compatible with 2.5 and forward
	- Internal clock frequency change to 2Mhz to support PkgC6 fast wake fix
	- Updated Modular CPLD code will connect PM_FAST_WAKE_N signal between all 4 socket of both Legacy and Non-Legacy nodes. 
    - Modular CPLD code simplifies ADR_TRIGGER logic 	
	  
========
[Global]
========
Rev00.0D - PLD revision number for Global CPLD