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Multi-Core Intel(R) Xeon(R) Processor-Based Server PLD Development
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INTEL Enterprise Products and Services Division
Intel Corporation
2111 N.E. 25th Avenue, Hillsboro, OR 97124 USA

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DATE    : December 6, 2019
TO      : Multi-Core Intel(R) Xeon(R) Processor-Based Server Platform customers
SUBJECT : Whitley Main PLD for Whitley Platform based, Common Core code included

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                           LEGAL INFORMATION
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Information in this document is provided in connection with Intel Products
and for the purpose of supporting Intel developed server boards and systems.
No license, express or implied, by estoppel or otherwise, to any intellectual 
property rights is granted by this document. Except as provided in Intel's 
Terms and Conditions of Sale for such products, Intel assumes no liability 
whatsoever, and Intel disclaims any express or implied warranty, relating to 
sale and/or use of Intel products including liability or warranties relating 
to fitness for a particular purpose, merchantability, or infringement of any 
patent, copyright or other intellectual property right. Intel Corporation 
may have patents or pending patent applications, trademarks, copyrights, or
other intellectual property rights that relate to the presented subject matter.
The furnishing of documents and other materials and information does not 
provide any license, express or implied, by estoppel or otherwise, to any such
patents, trademarks, copyrights, or other intellectual property rights.  
Intel products are not intended for use in medical, life saving, or life 
sustaining applications. Intel may make changes to specifications and product
descriptions at any time, without notice.

Intel is a registered trademark of Intel Corporation. 

*Other names and brands are the property of their respective owners.

Copyright (C) 2019 Intel Corporation.


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				INSTALLATION NOTES
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ATTENTION: 

Please use the TOPs intructions (doc#:610436) to correctly program the CPLD/FPGA's.
Use FPGA JTAG Cable (Altera Blaster II) to burn the .pof image into FPGA chip.

Please subsrcibe to obtain the Whitley BKC list at https://targetmailer.intel.com/subscriptions/#/30?cat=109 for the latest Main CPLD image release.


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				KNOWN ISSUES/WORKAROUND
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- PLD timing was addressed from Whitley PDG. Power rails from the CPU are on before asserting the PCH PWROK. The SYS_PWROK signal depends directly on PCH_PWROK. 
The PROC_PWRGD signal is the same as PWRGD_CPUPWRGD. No issues with booting platform.

- The Fab 2 board PLD image is not backwards compatiable with a Fab 1 board due to pinout changes from Fab 1 to Fab 2.

- 0x04 image contained clear CMOS and VR SMBus connections errors. 0x02.pof(Fab 1) and Main_non_pfr.pof(Fab 2) fixes these issues.

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				UPDATE
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[Main CPLD]

Rev00.00 - PLD revision number for Main CPLD

Rev00.05 addition

	- CPLD update to fix minor issues related with: ONCTL, CPUPWRGD, PWRBTN and PFR SMBus by-pass module.
	- PFR RoT enabled:
		- Updated timing to use PCH and BMC constraints from device datahseets. Added some additional reporting paths. Updated monitor interfaces to do timing on clock_fall.
		- New system console script to help read SPI contents.
		- Enabled SPI filter in provisioned mode. Added checks in unittest to make sure SPI/SMBus filters are enabled in provisioned T0 mode. 
		- Parameter added to allow user to choose ecdsa authentication result when EC block is disabled. Default value is EC authentication return failure.
	


[Debug CPLD]

Rev00.01 - PLD revision number for Main CPLD

	- Release for Debug CPLD located on Wilson City Baseboard.