Document Number:  620548-1.0 

 

 

 

 

 

 

 

Tiger Island 

 

Schematics PDF – FAB A 

 

March 2020 

 

Intel Confidential 

 

 

 

 

 

Important Notice:

 

 

1.

 

The content of this document is still under development and the product has 

yet to be verified. The information provided here is subject to 

change/modification in the next release. 

 

2.

 

The final version of the document will be available after the product has been 

validated. 

 

 

 

 

 

 

 

 

 

 

 
 
 

 

Tiger Island 

 

March 2020 

Schematics PDF

 

Intel Confidential

 

Document Number: 620548-1.0 

 

 

 

 

 

 

 

 

 

 

You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products 

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Copyright © 2020, Intel Corporation. All rights reserved. 

 

 

 

 
 
 

 

 

 

March 2020 

 

Tiger Island 

Document Number: 620548-1.0

 

Intel Confidential

 

Schematics PDF 

Revision History 

 

Date 

Revision 

Description 

March 2020 

0.5 

Initial release.   

 

 

§ 

 

 

 

 

 

 

 

 

 

 

PBA : K56089-100

PB  : K56090-100

REV:  1.00

TIGER ISLAND

TA  : K56088-100

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LB5G2

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LB7G1

LB4K1

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WEEE_LABEL_9X5MM

SERIAL_NUMBER

SILKSCREEN

LABEL

MAC_ADDRESS

LABEL

MAC_ADDRESS

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LEGAL STATEMENT

SVID JUMPERS

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1

CHANGELOG

PWR : SEQUENCE II/GLITCH FREE

PWR : SEQUENCE I

PWR : VCCST/VCCSTG

PWR : LAN RAIL

PWR : V12_S/V5_S/V3P3_S/V1P8_S

PWR : VCCIN PH2

PWR : VCCIN PH1

PWR : VCCIN

PWR : VNN/V1P05_A BYPASS

PWR : VCCIN_AUX

PWR : VDDQ_VPP

PWR : VDDQ_MEM/VDDQ_VTT

PWR : V1P8_A

PWR : V5_A/V3P3_A

PWR : V12_IN/RTC/BTN

B2B CONN : 80 PIN IO B2B

MISC : HDR/LEDS/FAN

SIO : RS485 HEADER

SIO : RS232 HEADER

SIO : F81804U

HDA : AUDIO JACK

HDA : ALC662_VD

SATA & ESATA : SATA PORT/PWR HDR

USB 3.1 : STACKED STD CONN X2

USB 3.1 : CMC & ESD 2

USB 3.1 : CMC & ESD 1

RJ45 :  RJ45 STACKED CONN

PHY : 88E2110 PWR

PHY : 88E2110

GBE : I225 FOXVILLE

M.2 KEY B : NANO SIM SLOT

M.2 KEY B : SLOT

M.2 KEY E : CLINK, RF_KILL

M.2 KEY E : SLOT

LVDS : PWR & HDR

LVDS : DDI SIGNALS

DP++ : STD  CONN

DP++ : CMC/ESD

HDMI : HDMI CMC/ESD & CONN

HDMI : HDMI ALS

SPI : TPM 2.0

SPI : FLASH & HDR

SPI : FLASH FET SWITCH

SODIMM CH1 : PWR DECAP

SODIMM CH1 : CONN 2

SODIMM CH1 : CONN2

SODIMM CH0 : PWR DECAP

SODIMM CH0 : CONN 1

SODIMM CH0 : CONN 1

STRAP : PCH STRAPS 3

STRAP : PCH STRAPS 2

STRAP : PCH STRAPS 1

STRAP : CPU STRAPS 2

STRAP : CPU STRAPS 1

DECAP : VDD2

DECAP : VCCIN_AUX/CCST/VCCSTG

DECAP: VCCIN

CPU : JTAG/MISC

CPU : XDP/FIVR DEBUG

CPU : GND

CPU : PCH POWER

CPU : CPU POWER

CPU : VCCIN

CPU : SYS PWR MANAGEMENT

CPU : PCIE CLOCK

CPU : CNV/CSI

CPU : PCIE/USB/SATA

CPU : AUDIO HDA/I2S

CPU : I2C/UART/SPI

CPU : SPI/SMB/SML/ESPI

CPU : MEMORY CH1

CPU : MEMORY CH0

CPU : DISPLAY

POWER SEQUENCE DIAGRAM

POWER MAP

BLOCK DIAGRAM

TABLE OF CONTENTS

LEGAL STATEMENT

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TABLE OF CONTENTS

SHEET NAME

SHEET NUMBER

SHEET NAME

TABLE OF CONTENTS

SHEET NUMBER

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TABLE - LED, KEY JUMPERS, SWITCHES, EC ERROR CODE

POWER MAP

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TABLE - LED, KEY JUMPERS, SWITCHES, EC ERROR CODE

POWER SEQUENCE DIAGRAM

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NC

NC

NC

STD DP

SPACING 380UM

TC_RCOMP MAIN ROUTE TRACE

STD HDMI 1

B2B

LVDS

DDIA_RCOMP MAIN ROUTE TRACE
SPACING 380UM

CPU : DISPLAY

SET PIN DK45 AS GPIO

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1

TP4P3

1

TP4P2

2

1

R4P4

2

1

R6C2

2

1

R6C3

DM8

AN2
AN1

BK1

BJ2

BK2

BJ1
BM7

BH5

BM5

BH7
BK5
BK7

BF1

BE2

BF2

BE1
BD7

AY5

BD5

AY7
BB5
BB7

AT2

AU1

AT1

AU2
AD5

AH7

AD7

AH5
AF7
AF5

AY2

BB1

AY1

BB2
AM5

AT7

AM7

AT5
AP7
AP5

DK27

DM29

DT6

DN4

DD6

DF6

DV8

DU8

DR5

DN21

DK23

DM23

DN23

DJ47

DG47

DF47

DF45

DG43

DF43

DK45

DH52

M8

CE4

T12

Y11

T9

V11

T11

Y9

P9

V9

AB9

AD9

AC2

AD2

AF1

AG2

AC1

AD1

AF2

AG1

AB1

AJ2
AJ1

DN8

DG10

U5E1

45B8 

64B3 

29B2 

29B5 

64A8 

40B6 
43A6 

64A8 

30B5 

43C8 

43C5 

30B8 

40B6 

40B6 

44C8 
44C8 

64C3 

64C3 

64A8 

64A8 

64C3 

64C3 

64C3 

64C3 

40B6 

42A8 
42A8 

64C3 

43C8 

64C3 

40B6 

42B8 

43C5 

42D8 

42D8 

42B8 

42C8 

42C8 

40B6 

40B6 

40B6 

40B6 

40B6 

40B6 

44B8 

44B8 

44C8 

44D8 

44D8 

BMAP_REV=1.2

TGL_U_IP

SOC

LPID6529

1 OF 21

150
1%
CH
0402LF
1/16W

1%

CH

0402LF

150

CH

5%

100K

0402LF

TP

TP

DDIA_BKLTCTL

DDSP_HPD3

GPPC_D12_DDP4_SDA

GPPC_D10_DDP3_SDA

DDSP_HPD1
DDSP_HPD2

GPPC_D9_DPP3_SCL

GPPC_E21_DDP2_SDA

GPPC_E20_DDP2_SCL

GPPC_E19_DDP1_SDA

GPPC_E18_DDP1_SCL

DDIA_TX1_DP
DDIA_TX1_DN

DDIA_RCOMP

TC_RCOMPN

TC_RCOMPP

TCP2_TX1_DN

TCP2_TXRX1_DN

DSI_DE_TE_2

TCP2_AUX_DN

TCP2_AUX_DP

TCP2_TX0_DN

TCP2_TX0_DP

TCP2_TX1_DP

TCP2_TXRX1_DP

DDI1_HDMI_DATA2_DN
DDI1_AUX_DP
DDI1_AUX_DN

DDI2_DP_LANE3_DP
DDI2_DP_LANE3_DN

TCP2_TXRX0_DN

DDI2_DP_AUX_DN

TCP2_TXRX0_DP

DDI1_HDMI_DATA2_DP

DDI2_DP_LANE2_DN

DDI2_DP_AUX_DP

DDI2_DP_LANE0_DN

DDI2_DP_LANE0_DP

DDI2_DP_LANE2_DP

DDI2_DP_LANE1_DN

DDI2_DP_LANE1_DP

DDI1_HDMI_DATA0_DN

DDI1_HDMI_DATA0_DP

DDI1_HDMI_DATA1_DN

DDI1_HDMI_DATA1_DP

DDI1_HDMI_CLK_DN

DDI1_HDMI_CLK_DP

DDPA_HPD

DDIA_AUX_DN

DDIA_AUX_DP

DDIA_TX0_DN

DDIA_TX0_DP

CPU : DISPLAY

DESIGN NOTE:

INTEL CORPORATION

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CAD NOTE:

CAD NOTE:

DESIGN NOTE:

BI

BI

IN

IN

DISP_UTILS

DDIA_RCOMP

DSI_DE_TE_2

TCRCOMPN

TCRCOMPP

TCP3_AUXPAD_N

TCP3_AUXPAD_P

TCP3_TX_N0

TCP3_TX_P0

TCP3_TX_N1

TCP3_TX_P1

TCP3_TXRX_N0

TCP3_TXRX_P0

TCP3_TXRX_N1

TCP3_TXRX_P1

TCP2_AUXPAD_N

TCP2_AUXPAD_P

TCP2_TX_N0

TCP2_TX_P0

TCP2_TX_N1

TCP2_TX_P1

TCP2_TXRX_N0

TCP2_TXRX_P0

TCP2_TXRX_N1

TCP2_TXRX_P1

TCP1_AUXPAD_N

TCP1_AUXPAD_P

TCP1_TX_N0

TCP1_TX_P0

TCP1_TX_N1

TCP1_TX_P1

TCP1_TXRX_N0

TCP1_TXRX_P0

TCP1_TXRX_N1

TCP1_TXRX_P1

TCP0_AUXPAD_N

TCP0_AUXPAD_P

TCP0_TX_N0

TCP0_TX_P0

TCP0_TX_N1

TCP0_TX_P1

TCP0_TXRX_N0

TCP0_TXRX_P0

TCP0_TXRX_N1

TCP0_TXRX_P1

BKLTCTL

BKLTEN

VDDEN

GPPC_A_15_USB2_OCB_2_DDSP_HPD_4_I2S4_SCLK_DISP_MISC_4

GPPC_A_14_USB2_OCB_1_DDSP_HPD_3_I2S3_RXD_DISP_MISC_3_DMIC_CLK_B_1

GPPC_A_20_DDSP_HPD_2_DISP_MISC_2_I2S5_SFRM

GPPC_A_19_DDSP_HPD_1_DISP_MISC_1_I2S5_SCLK

GPPC_A_17_DISP_MISC_C_I2S4_TXD

GPPC_D_12_ISH_SPI_MOSI_DDP4_CTRLDATA_CAS_SPIM_MOSI_TBT_LSX3_B_GSPI2_MOSI_CAS_SPIS_MOSI

GPPC_D_11_ISH_SPI_MISO_DDP4_CTRLCLK_CAS_SPIM_MISO_TBT_LSX3_A_GSPI2_MISO_CAS_SPIS_MISO

GPPC_D_10_ISH_SPI_CLK_DDP3_CTRLDATA_CAS_SPIM_CLK_TBT_LSX2_B_GSPI2_CLK_CAS_SPIS_CLK

GPPC_D_9_ISH_SPI_CSB_DDP3_CTRLCLK_CAS_SPIM_CS0B_TBT_LSX2_A_GSPI2_CS0B_CAS_SPIS_CSB

GPPC_E_21_DDP2_CTRLDATA_TBT_LSX1_B

GPPC_E_20_DDP2_CTRLCLK_TBT_LSX1_A

GPPC_E_19_DDP1_CTRLDATA_TBT_LSX0_B

GPPC_E_18_DDP1_CTRLCLK_TBT_LSX0_A

GPPC_A_22_DDPC_CTRLDATA_I2S5_RXD

GPPC_A_21_DDPC_CTRLCLK_I2S5_TXD

GPPC_A_18_DDSP_HPD_B_DISP_MISC_B_I2S4_RXD

GPPC_H_17_DDPB_CTRLDATA

GPPC_H_16_DDPB_CTRLCLK_PCIE_LNK_DOWN

DDIB_AUXN

DDIB_AUXP

DDIB_TXN_0

DDIB_TXP_0

DDIB_TXN_1

DDIB_TXP_1

DDIB_TXN_2

DDIB_TXP_2

DDIB_TXN_3

DDIB_TXP_3

GPPC_E_14_DDSP_HPD_A_DISP_MISC_A

GPPC_E_23_DDPA_CTRLDATA

GPPC_E_22_DDPA_CTRLCLK_DNX_FORCE_RELOAD

DDIA_AUXN

DDIA_AUXP

DDIA_TXN_0

DDIA_TXP_0

DDIA_TXN_1

DDIA_TXP_1

DDIA_TXN_2

DDIA_TXP_2

DDIA_TXN_3

DDIA_TXP_3

BI

BI

BI
BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

T_POINT1
T_POINT1

OUT

OUT

OUT
OUT
OUT

OUT

OUT

OUT

OUT
OUT

OUT

BI

OUT

BI

IN

BI
BI

BI
BI

IN

BI

 

 

CPU : MEMORY CH0

NC

NC

TP

DDR_COMP MAIN ROUTE TRACE SPACING 500UM

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2

1

R6T12

2

1

R6T10

2

1

R7F1

DV47

BB44

BK44

CK44

CT44

BA51

BG51

CK51

CR51

BD44

BH44

CM44

CV44

BA50

BG50

CK50

CR50

BD47

BB47

BD45

BB45
BB42
BB41

BD42
BD41

BK47
BK45

BH47
BH45
BH42

BK42
BK41

BH41

CK47

CM47

CK45

CM45

CK42

CM42
CM41

CK41

CT47

CV47

CT45

CV45

CT42

CV42

CT41

CV41

AY53
AY52
AY50
AY49

BC53
BC52
BC50
BC49

BF53
BF52
BF50
BF49

BH53
BH52
BH50
BH49

CH53
CH52
CH50
CH49

CL53
CL52
CL50
CL49

CP53
CP52
CP50
CP49

CU53
CU52
CU50
CU49

E52

BT47

BT45

BP47
BP42
BP45
BP44

BL53

BP52
BP53

BN53

BN51

CD42
CD41

CD47

CD45

CA53

CA51

CE50

CE53

C49

BV45

CF44
CF45

CB47
CB44
CB45
CF41
BU53
BT51
BV42
BU50
BY53
CA50
BY52
BY50
CD51
CD53
BV47
CE52
BV41

CF42
CF47

BT42

CC52

BT41

CC53

BU52
BL50

BN50
BL52

CB42
BV44

BT53

AU49

AU50

U5E1

31C7 

31B4 

31A5  34A5  31B7 
34B7 

31A4 

31B4 

31B4 

31C4 

31D4 

31B4 

31C4 

31B1 
31B1 
31B1 
31B1 

31C1 

31C7 
31C7 

31C7 
31C7 

31C7 

31C7 
31C7 

31B1 
31B1 
31B1 
31B1 
31C1 

31C1 
31C1 
31B1 
31C1 
31C1 

31C7 

31C7 

31C7 

31C7 

31C1 

31C7 

31C7 

31B7 

31B7 

31B7 

32C5 

68A5 

31D4 

31C4 

31C4 

31D8 

VDDQ_MEM

SOC

TGL_U_IP

BMAP_REV=1.2

2 OF 21

LPID6529

100
1%
CH
0402LF
1/16W

0402LF CH

5%

0

1/16W

0402LF

5%

470

CH

M_0_BG0

M_0_DQ_6<7..0>

DRAM_RESET_N_R

M_0_DQ_7<7..0>

M_0_DQ_5<7..0>

6

M_0_DQ_3<7..0>

6

M_0_DQ_4<7..0>

6

M0_3CA4
M0_3CA3
M0_3CA2

M_0_DQS_7_DP
M_0_DQS_7_DN
M_0_DQS_6_DP
M_0_DQS_6_DN

M_0_DQS_2_DP

M_0_CLK_DDR1_DP
M_0_CLK_DDR1_DN

M0_2CLK_DP
M0_2CLK_DN
M0_1CLK_DP
M0_1CLK_DN

M_0_CLK_DDR0_DP
M_0_CLK_DDR0_DN

M0_3CKE0

M0_2CKE0
M0_2CKE1
M0_1CKE0
M0_1CKE1
M0_0CKE0

M_0_CKE_0

M_0_CS1_N
M_0_CS0_N

M0_0CA0
M0_0CA1
M0_2CS0
M0_3CA5

M_0_DQS_5_DP
M_0_DQS_5_DN
M_0_DQS_4_DP
M_0_DQS_4_DN
M_0_DQS_3_DP

M_0_DQS_2_DN
M_0_DQS_1_DP
M_0_DQS_1_DN
M_0_DQS_0_DP
M_0_DQS_0_DN

M_0_ODT0

M_0_BG1

M_0_BA1

DDR_COMP_0

M_0_CKE_1

M0_0CKE1

M0_3CKE1

M_0_DQS_3_DN

M_0_ODT1

M_0_BA0

M_0_ACT_N

M_0_PARITY

M_0_ALERT_N
V_DDR0_VREF_CA

DDR_VTT_CTRL

DRAM_RESET_N

M_0_DQ_2<7..0>

M_0_DQ_1<7..0>

M_0_DQ_0<7..0>

M_0_MA<16..0>

CPU : MEMORY CH0

0

1

2

3

4

5

6

8
7

9

12
11
10

13

14

15

16

7
6
5
4
3
2
1
0

7
6
5
4
3
2
1
0

0

1

2

3

4

5

7

0

1

2

3

4

5

7

0

1

2

3

4

5

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

3
2
1
0

5
4

6

7

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE: 

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

BI

OUT

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

OUT

BI

BI

BI

OUT

OUT

IN

BI

OUT

OUT

OUT

BI
BI
BI

DDR_COMP

DRAM_RESETB

DDR_VTT_CTL

DDR0_VREF_CA

DDR0_ALERT_N

DDR_0PAR_3CS1_3CS0_3CA3

DDR_0ACTN_2CS1_2CS0_2CA3

DDR_0BA0_3CA0_3CA0_3CA6

DDR_0BA1_1CA5_1CA6_1CA0

DDR_0BG0_2CA3_2CA4_2CS1

DDR_0BG1_2CA2_2CA3_2CS0

DDR_0MA0_NC_3CS1_3CA4

DDR_0MA1_NC_0CS1_0CA4

DDR_0MA2_3CS0_3CA2_3CA2

DDR_0MA3_0CS1_0CS0_0CA3

DDR_0MA4_0CS0_0CA2_0CA2

DDR_0MA5_0CA5_0CA6_0CA0

DDR_0MA6_0CA3_0CA4_0CS1

DDR_0MA7_0CA4_0CA5_0CA1

DDR_0MA8_0CA2_0CA3_0CS0

DDR_0MA9_2CA0_2CA0_2CA6

DDR_0MA10_3CA1_3CA1_3CA5

DDR_0MA11_NC_2CS1_2CA4

DDR_0MA12_2CA1_2CA1_2CA5

DDR_0MA13_1CS1_1CS0_1CA3

DDR_0MA14_1CA2_1CA3_1CS0

DDR_0MA15_1CA3_1CA4_1CS1

DDR_0MA16_1CA4_1CA5_1CA1

DDR_0ODT0_1CS0_1CA2_1CA2

DDR_0ODT1_1CA0_1CA0_1CA6

DDRDQSN_IL00_NIL00_LP00

DDRDQSP_IL00_NIL00_LP00

DDRDQSN_IL01_NIL01_LP01

DDRDQSP_IL01_NIL01_LP01

DDRDQSN_IL10_NIL02_LP10

DDRDQSP_IL10_NIL02_LP10

DDRDQSN_IL11_NIL03_LP11

DDRDQSP_IL11_NIL03_LP11

DDRDQSN_IL02_NIL04_LP20

DDRDQSP_IL02_NIL04_LP20

DDRDQSN_IL03_NIL05_LP21

DDRDQSP_IL03_NIL05_LP21

DDRDQSN_IL12_NIL06_LP30

DDRDQSP_IL12_NIL06_LP30

DDRDQSN_IL13_NIL07_LP31

DDRDQSP_IL13_NIL07_LP31

DDR_NC_3CA2_3CA3_3CS0

DDR_NC_3CA3_3CA4_3CS1

DDR_NC_3CA4_3CA5_3CA1

DDR_NC_3CA5_3CA6_3CA0

DDR_NC_2CS0_2CA2_2CA2

DDR_NC_0CA1_0CA1_0CA5

DDR_NC_0CA0_0CA0_0CA6

DDR_0CS0_NC_1CS1_1CA4

DDR_0CS1_1CA1_1CA1_1CA5

DDR_0CKE0_2CA5_2CA6_2CA0

DDR_0CKE1_2CA4_2CA5_2CA1

DDR_NC_0CKE1_0WCKN_0WCKN

DDR_NC_0CKE0_0WCKP_0WCKP

DDR_NC_1CKE1_1WCKN_1WCKN

DDR_NC_1CKE0_1WCKP_1WCKP

DDR_NC_2CKE1_2WCKN_2WCKN

DDR_NC_2CKE0_2WCKP_2WCKP

DDR_NC_3CKE1_3WCKN_3WCKN

DDR_NC_3CKE0_3WCKP_3WCKP

DDR_0CLKN0_0CLKN_0CLKN_0CLKN

DDR_0CLKP0_0CLKP_0CLKP_0CLKP

DDR_NC_1CLKN_1CLKN_1CLKN

DDR_NC_1CLKP_1CLKP_1CLKP

DDR_NC_2CLKN_2CLKN_2CLKN

DDR_NC_2CLKP_2CLKP_2CLKP

DDR_0CLKN1_3CLKN_3CLKN_3CLKN

DDR_0CLKP1_3CLKP_3CLKP_3CLKP

DDRDQ_IL13_NIL07_LP31_0

DDRDQ_IL13_NIL07_LP31_1

DDRDQ_IL13_NIL07_LP31_2

DDRDQ_IL13_NIL07_LP31_3

DDRDQ_IL13_NIL07_LP31_4

DDRDQ_IL13_NIL07_LP31_5

DDRDQ_IL13_NIL07_LP31_6

DDRDQ_IL13_NIL07_LP31_7

DDRDQ_IL12_NIL06_LP30_0

DDRDQ_IL12_NIL06_LP30_1

DDRDQ_IL12_NIL06_LP30_2

DDRDQ_IL12_NIL06_LP30_3

DDRDQ_IL12_NIL06_LP30_4

DDRDQ_IL12_NIL06_LP30_5

DDRDQ_IL12_NIL06_LP30_6

DDRDQ_IL12_NIL06_LP30_7

DDRDQ_IL03_NIL05_LP21_0

DDRDQ_IL03_NIL05_LP21_1

DDRDQ_IL03_NIL05_LP21_2

DDRDQ_IL03_NIL05_LP21_3

DDRDQ_IL03_NIL05_LP21_4

DDRDQ_IL03_NIL05_LP21_5

DDRDQ_IL03_NIL05_LP21_6

DDRDQ_IL03_NIL05_LP21_7

DDRDQ_IL02_NIL04_LP20_0

DDRDQ_IL02_NIL04_LP20_1

DDRDQ_IL02_NIL04_LP20_2

DDRDQ_IL02_NIL04_LP20_3

DDRDQ_IL02_NIL04_LP20_4

DDRDQ_IL02_NIL04_LP20_5

DDRDQ_IL02_NIL04_LP20_6

DDRDQ_IL02_NIL04_LP20_7

DDRDQ_IL11_NIL03_LP11_0

DDRDQ_IL11_NIL03_LP11_1

DDRDQ_IL11_NIL03_LP11_2

DDRDQ_IL11_NIL03_LP11_3

DDRDQ_IL11_NIL03_LP11_4

DDRDQ_IL11_NIL03_LP11_5

DDRDQ_IL11_NIL03_LP11_6

DDRDQ_IL11_NIL03_LP11_7

DDRDQ_IL10_NIL02_LP10_0

DDRDQ_IL10_NIL02_LP10_1

DDRDQ_IL10_NIL02_LP10_2

DDRDQ_IL10_NIL02_LP10_3

DDRDQ_IL10_NIL02_LP10_4

DDRDQ_IL10_NIL02_LP10_5

DDRDQ_IL10_NIL02_LP10_6

DDRDQ_IL10_NIL02_LP10_7

DDRDQ_IL01_NIL01_LP01_0

DDRDQ_IL01_NIL01_LP01_1

DDRDQ_IL01_NIL01_LP01_2

DDRDQ_IL01_NIL01_LP01_3

DDRDQ_IL01_NIL01_LP01_4

DDRDQ_IL01_NIL01_LP01_5

DDRDQ_IL01_NIL01_LP01_6

DDRDQ_IL01_NIL01_LP01_7

DDRDQ_IL00_NIL00_LP00_0

DDRDQ_IL00_NIL00_LP00_1

DDRDQ_IL00_NIL00_LP00_2

DDRDQ_IL00_NIL00_LP00_3

DDRDQ_IL00_NIL00_LP00_4

DDRDQ_IL00_NIL00_LP00_5

DDRDQ_IL00_NIL00_LP00_6

DDRDQ_IL00_NIL00_LP00_7

BI

BI

OUT

OUT

OUT

OUT

OUT

BI
BI

BI

BI

BI

BI

 

 

CPU : MEMORY CH1

CR-9 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE9

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 9 OF 80

INTEL CONFIDENTIAL
<>

K36

G44

AJ44

AV44

D39

C45

AG51

AN51

K38

J44

AL44

AR44

C39

D45

AG50

AN50

G38
G36

H36
H38
N36

L36
L38

N38

G42
G41

J41
J42

G45

J45

G47

J47

AJ41
AJ42

AL41
AL42

AJ45
AJ47

AL45
AL47

AR41

AV42

AR42

AV41

AR45

AV45

AR47

AV47

E38

D38

B38
A38
E41

D40

B40
A40

A43
B43

D43

E44
A46
B46

D46

E47

AF53
AF52
AF50
AF49

AH53
AH52
AH50
AH49

AL53
AL52
AL50
AL49

AP53
AP52
AP50
AP49

R45

R47

N42
N45
N44
N47
J53

M52
M53

K53

K51

AC42
AC41

AC45

AC47

W53

W51

AC50
AC53

U45

AE44
AE45

AA47
AA44
AA45
AE41
P53
N51
U42
P50
U53
W50
U52
U50
AA51
AA53
U47
AC52
U41

AE42
AE47

R41

Y52

R42

Y53

P52
J50

K50
J52

AA42
U44

N53

AU52

AU53

U5E1

34B4 

34A4 

34B4 

34C4 

34D4 

34B4 

34B4 

34C4 

34C1 
34C1 

34C7 

34C7 
34C7 

34C7 

34C7 

34C7 

34B1 

34B1 

34B1 

34B1 
34B1 
34B1 
34B1 
34B1 

34B1 

34C1 

34C1 

34C1 

34C1 

34B1 

34C7 

34C7 
34C7 

34B7 

34B7 

34B7 

34C7 

34C7 
34C7 

34C7 

35C5 

34C7 

34C4 

34C4 

34D4 

34D8 

3 OF 21

SOC

TGL_U_IP

BMAP_REV=1.2

LPID6529

M_1_DQ_4<7..0>

M_1_DQ_5<7..0>

6

M_1_DQ_3<7..0>

6

6

M_1_DQ_7<7..0>

M_1_DQ_6<7..0>

M1_0CA1

M1_2CS0

M1_3CA2

M1_0CKE1

M1_0CKE0

M1_1CKE1

M1_1CKE0

M1_2CKE1

M1_3CKE1

M1_3CKE0

M1_1CLK_DN

M1_1CLK_DP

M1_2CLK_DN

M1_2CLK_DP

M1_3CA3

M1_2CKE0

M1_0CA0

M1_3CA4

M1_3CA5

M_1_DQS_0_DP
M_1_DQS_0_DN

M_1_ODT1

M_1_CLK_DDR0_DP
M_1_CLK_DDR0_DN

M_1_CLK_DDR1_DN

M_1_CLK_DDR1_DP

M_1_CKE_1

M_1_DQS_6_DP

M_1_DQS_7_DN

M_1_DQS_7_DP

M_1_DQS_6_DN
M_1_DQS_5_DP
M_1_DQS_5_DN
M_1_DQS_4_DP
M_1_DQS_4_DN

M_1_DQS_1_DP

M_1_DQS_2_DP

M_1_DQS_3_DN

M_1_DQS_3_DP

M_1_DQS_2_DN

M_1_DQS_1_DN

M_1_CKE_0

M_1_CS1_N
M_1_CS0_N

M_1_PARITY

M_1_ALERT_N

M_1_ACT_N

M_1_BG1

M_1_BA1
M_1_BA0

M_1_BG0

V_DDR1_VREF_CA

M_1_ODT0

M_1_DQ_0<7..0>

M_1_DQ_1<7..0>

M_1_DQ_2<7..0>

M_1_MA<16..0>

CPU : MEMORY CH1

4
3
2
1
0

7
6
5
4
3

0

1

2

7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7

5
4
3
2
1
0
7

5
4
3
2
1
0
7

5
4
3
2
1
0
7

5

6

2

3

4

0

1

5

6

7

16
15
14
13
12
11

8

9

10

7
6
5
4
3
2
1
0

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE: 

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

BI

BI

BI
BI
BI

BI

BI

BI

BI

BI

BI

BI
BI
BI

OUT

OUT
OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

DDR1_VREF_CA

DDR1_ALERT_N

DDR_1PAR_7CS1_7CS0_7CA3

DDR_1ACTN_6CS1_6CS0_6CA3

DDR_1BA0_7CA0_7CA0_7CA6

DDR_1BA1_5CA5_5CA6_5CA0

DDR_1BG0_6CA3_6CA4_6CS1

DDR_1BG1_6CA2_6CA3_6CS0

DDR_1MA0_NC_7CS1_7CA4

DDR_1MA1_NC_4CS1_4CA4

DDR_1MA2_7CS0_7CA2_7CA2

DDR_1MA3_4CS1_4CS0_4CA3

DDR_1MA4_4CS0_4CA2_4CA2

DDR_1MA5_4CA5_4CA6_4CA0

DDR_1MA6_4CA3_4CA4_4CS1

DDR_1MA7_4CA4_4CA5_4CA1

DDR_1MA8_4CA2_4CA3_4CS0

DDR_1MA9_6CA0_6CA0_6CA6

DDR_1MA10_7CA1_7CA1_7CA5

DDR_1MA11_NC_6CS1_6CA4

DDR_1MA12_6CA1_6CA1_6CA5

DDR_1MA13_5CS1_5CS0_5CA3

DDR_1MA14_5CA2_5CA3_5CS0

DDR_1MA15_5CA3_5CA4_5CS1

DDR_1MA16_5CA4_5CA5_5CA1

DDR_1ODT0_5CS0_5CA2_5CA2

DDR_1ODT1_5CA0_5CA0_5CA6

DDRDQSN_IL04_NIL10_LP40

DDRDQSP_IL04_NIL10_LP40

DDRDQSN_IL05_NIL11_LP41

DDRDQSP_IL05_NIL11_LP41

DDRDQSN_IL14_NIL12_LP50

DDRDQSP_IL14_NIL12_LP50

DDRDQSN_IL15_NIL13_LP51

DDRDQSP_IL15_NIL13_LP51

DDRDQSN_IL06_NIL14_LP60

DDRDQSP_IL06_NIL14_LP60

DDRDQSN_IL07_NIL15_LP61

DDRDQSP_IL07_NIL15_LP61

DDRDQSN_IL16_NIL16_LP70

DDRDQSP_IL16_NIL16_LP70

DDRDQSN_IL17_NIL17_LP71

DDRDQSP_IL17_NIL17_LP71

DDR_NC_4CA0_4CA0_4CA6

DDR_NC_4CA1_4CA1_4CA5

DDR_NC_6CS0_6CA2_6CA2

DDR_NC_7CA2_7CA3_7CS0

DDR_NC_7CA3_7CA4_7CS1

DDR_NC_7CA4_7CA5_7CA1

DDR_NC_7CA5_7CA6_7CA0

DDR_1CS0_NC_5CS1_5CA4

DDR_1CS1_5CA1_5CA1_5CA5

DDR_1CKE0_6CA5_6CA6_6CA0

DDR_1CKE1_6CA4_6CA5_6CA1

DDR_NC_4CKE1_4WCKN_4WCKN

DDR_NC_4CKE0_4WCKP_4WCKP

DDR_NC_5CKE1_5WCKN_5WCKN

DDR_NC_5CKE0_5WCKP_5WCKP

DDR_NC_6CKE1_6WCKN_6WCKN

DDR_NC_6CKE0_6WCKP_6WCKP

DDR_NC_7CKE1_7WCKN_7WCKN

DDR_NC_7CKE0_7WCKP_7WCKP

DDR_1CLKN0_4CLKN_4CLKN_4CLKN

DDR_1CLKP0_4CLKP_4CLKP_4CLKP

DDR_NC_5CLKN_5CLKN_5CLKN

DDR_NC_5CLKP_5CLKP_5CLKP

DDR_NC_6CLKN_6CLKN_6CLKN

DDR_NC_6CLKP_6CLKP_6CLKP

DDR_1CLKN1_7CLKN_7CLKN_7CLKN

DDR_1CLKP1_7CLKP_7CLKP_7CLKP

DDRDQ_IL17_NIL17_LP71_0

DDRDQ_IL17_NIL17_LP71_1

DDRDQ_IL17_NIL17_LP71_2

DDRDQ_IL17_NIL17_LP71_3

DDRDQ_IL17_NIL17_LP71_4

DDRDQ_IL17_NIL17_LP71_5

DDRDQ_IL17_NIL17_LP71_6

DDRDQ_IL17_NIL17_LP71_7

DDRDQ_IL16_NIL16_LP70_0

DDRDQ_IL16_NIL16_LP70_1

DDRDQ_IL16_NIL16_LP70_2

DDRDQ_IL16_NIL16_LP70_3

DDRDQ_IL16_NIL16_LP70_4

DDRDQ_IL16_NIL16_LP70_5

DDRDQ_IL16_NIL16_LP70_6

DDRDQ_IL16_NIL16_LP70_7

DDRDQ_IL07_NIL15_LP61_0

DDRDQ_IL07_NIL15_LP61_1

DDRDQ_IL07_NIL15_LP61_2

DDRDQ_IL07_NIL15_LP61_3

DDRDQ_IL07_NIL15_LP61_4

DDRDQ_IL07_NIL15_LP61_5

DDRDQ_IL07_NIL15_LP61_6

DDRDQ_IL07_NIL15_LP61_7

DDRDQ_IL06_NIL14_LP60_0

DDRDQ_IL06_NIL14_LP60_1

DDRDQ_IL06_NIL14_LP60_2

DDRDQ_IL06_NIL14_LP60_3

DDRDQ_IL06_NIL14_LP60_4

DDRDQ_IL06_NIL14_LP60_5

DDRDQ_IL06_NIL14_LP60_6

DDRDQ_IL06_NIL14_LP60_7

DDRDQ_IL15_NIL13_LP51_0

DDRDQ_IL15_NIL13_LP51_1

DDRDQ_IL15_NIL13_LP51_2

DDRDQ_IL15_NIL13_LP51_3

DDRDQ_IL15_NIL13_LP51_4

DDRDQ_IL15_NIL13_LP51_5

DDRDQ_IL15_NIL13_LP51_6

DDRDQ_IL15_NIL13_LP51_7

DDRDQ_IL14_NIL12_LP50_0

DDRDQ_IL14_NIL12_LP50_1

DDRDQ_IL14_NIL12_LP50_2

DDRDQ_IL14_NIL12_LP50_3

DDRDQ_IL14_NIL12_LP50_4

DDRDQ_IL14_NIL12_LP50_5

DDRDQ_IL14_NIL12_LP50_6

DDRDQ_IL14_NIL12_LP50_7

DDRDQ_IL05_NIL11_LP41_0

DDRDQ_IL05_NIL11_LP41_1

DDRDQ_IL05_NIL11_LP41_2

DDRDQ_IL05_NIL11_LP41_3

DDRDQ_IL05_NIL11_LP41_4

DDRDQ_IL05_NIL11_LP41_5

DDRDQ_IL05_NIL11_LP41_6

DDRDQ_IL05_NIL11_LP41_7

DDRDQ_IL04_NIL10_LP40_0

DDRDQ_IL04_NIL10_LP40_1

DDRDQ_IL04_NIL10_LP40_2

DDRDQ_IL04_NIL10_LP40_3

DDRDQ_IL04_NIL10_LP40_4

DDRDQ_IL04_NIL10_LP40_5

DDRDQ_IL04_NIL10_LP40_6

DDRDQ_IL04_NIL10_LP40_7

BI

BI

BI

BI

BI

BI

 

 

10K OHM : 100 KHZ

499 OHM : 1 MHZ (DEFAULT)

PLACE RA CLOSE TO

RA

RA

PCH WITHIN 15MM

PLACE RA CLOSE TO

PCH WITHIN 15MM

RA

RA

CPU : SPI/SMB/SML/ESPI

PCH WITHIN 15MM

PLACE RA CLOSE TO

RA

RA

PLACE RA CLOSE TO

PCH 

RA

2.2K OHM : 400 MHZ

CR-10 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE10

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 10 OF 80

INTEL CONFIDENTIAL
<>

DV24

DW47
DW49

A48

U5E1

2

1

R2J2

2

1

R4G8

2

1

R4G1

2

1

R4F6

2

1

R6U2

2

1

R4F7

2

1

R4G10

1

TP6R8

2

1

R6P7

2

1

R6P8

2

1

R6P18

2

1

R6P17

2

1

R7P2

2

1

R6P9

DF39

DJ35

DJ33

DG35

DJ39

DF35

DG37

DJ37

DF2

DH4

DH3

DN10

DV14

DK15

DK13

DM13

DN13

DJ15

DN15

DW9

DK6

DM6

DJ6

DK8

DV11

DT8

DN5
DR9

DJ17

DK17

DN17

DM17

DK19

DN19

DM19

DK21

CY50

DL50

DN53

DK52

DJ53
DH50
DP50
DP52

U5E1

60C2  60C7 

10C2 

60A6  60C2  60C7 

10C2 

60C2  60C7 

10C2 

60C2  60B7 

10C2 

10C2 

60B2  60C7 

10C2 

60B2  60C7 

10C2 

60B2  60C7 

47C8 

47C8 

47C8 

51D8 

51B7 

51D8 

29C4 

28C5 

39B2 

10C2  50D7 

10C2 

10C2 

10B4 

37C8 
28B2 

37A8 

28C2 

37A8 

37C8 

10A5  32A2  40C6  64B8  44A5  57A7 
10A5  32A2  40C6  44A5  57A7  64B8 

10A7  50D7 
10A7  50D7 
30A5 

10A7 

10D2  50D7 

28B5 

37C8 

37A8 
37A8 

29C3 

65A4 

28A8  64B8 

10A4 

10A4 

30C8 

10A7 

10A4 

10A4 
10A4 
10B4 

10D2  32A2  40C6  44A5  57A7  64B8 
10D2  32A2  40C6  64B8  44A5  57A7 

V3P3_A

V3P3_A

V3P3_S

BMAP_REV=1.2

LPID6529

SOC

TGL_U_IP

5 OF 21

1%

499

0402LF
1/16W

CH

499
1%

1/16W

0402LF

CH

0402LF

CH

5%

1/16W

1K

0402LF
1/16W

1K

CH

5%

499

0402LF

1%
CH

1/16W

499

1/16W

0402LF

CH

1%

TP

1%

15

0402LF CH

1%

15

0402LF CH

1%

15

0402LF CH

1%

15

0402LF CH

1%

50

0402LF CH

0

0

0402LF CH

0

0

0402LF CH

LPID6529

SOC

BMAP_REV=1.2

TGL_U_IP

4 OF 21

SIO_ESPI_CS_N

GPPC_A4_ESPI_CS_N

SIO_ESPI_RST_N

GPPC_A6_ESPI_RST_N

SIO_ESPI_IO0

GPPC_A0_ESPI_IO_0

SIO_ESPI_CLK

GPPC_A5_ESPI_CLK

GPPC_A3_ESPI_IO_3

SIO_ESPI_IO1

GPPC_A1_ESPI_IO_1

SIO_ESPI_IO2

GPPC_A2_ESPI_IO_2

SIO_ESPI_IO3

CNV_WLAN_CLINK_RST_N

CNV_WLAN_CLINK_DATA

CNV_WLAN_CLINK_CLK

GPPC_F17_SGMII_MDC

GPPC_F18_SGMII_MDIO

GPPC_E10_SPI1_CS0_N

GPPC_E6_SPI1_RST_N

GPPC_E13_TPM_IRQ

SML0_DATA

SML1_CLK

SML1_DATA

GPPC_A6_ESPI_RST_N

SPI0_CLK
SPI0_IO_3
SPI0_IO_2
SPI0_MISO

SMB_SCL
SMB_SDA

SML0_CLK
SML0_DATA
GPPC_C5_SML0ALERT_N

SML1_CLK

SML0_CLK

CPU : SPI/SMB/SML/ESPI

SPI0_MOSI
SPI0_CS1_N
SPI0_CS0_N
SPI0_TPM_CS_N

GPPC_E11_SPI1_CLK_N

GPPC_E8_SATA_LED_N

GPPC_C2_SMBALERT_N

GPPC_A2_ESPI_IO_2

GPPC_A5_ESPI_CLK

GPPC_B23_SML1ALERT_N

SML1_DATA

GPPC_A3_ESPI_IO_3

GPPC_A1_ESPI_IO_1
GPPC_A0_ESPI_IO_0
GPPC_A4_ESPI_CS_N

SMB_SDA
SMB_SCL

CAD NOTE:

DESIGN NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE: 

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

CAD NOTE:

CAD NOTE:

GPPC_A_6_ESPI_RESETB

GPPC_A_4_ESPI_CSB

GPPC_A_0_ESPI_IO_0

GPPC_A_1_ESPI_IO_1

GPPC_A_2_ESPI_IO_2_SUSWARNB_SUSPWRDNACK

GPPC_A_3_ESPI_IO_3_SUSACKB

GPPC_A_5_ESPI_CLK

GPPC_B_23_SML1ALERTB_PCHHOTB_GSPI1_CS1B

GPPC_C_7_SML1DATA

GPPC_C_6_SML1CLK

GPPC_C_5_SML0ALERTB

GPPC_C_4_SML0DATA

GPPC_C_3_SML0CLK

GPPC_C_2_SMBALERTB

GPPC_C_1_SMBDATA

GPPC_C_0_SMBCLK

MLK_RSTB

MLK_DATA

MLK_CLK

GPPC_F_17_GMII_MDC_THC1_SPI2_RSTB

GPPC_F_18_GMII_MDIO_THC1_SPI2_INTB

GPPC_F_16_GSXCLK_THC1_SPI2_CSB

GPPC_F_12_GSXDOUT_THC1_SPI2_IO_0

GPPC_F_13_GSXSLOAD_THC1_SPI2_IO_1

GPPC_F_14_GSXDIN_THC1_SPI2_IO_2

GPPC_F_15_GSXSRESETB_THC1_SPI2_IO_3

GPPC_F_11_THC1_SPI2_CLK

GPPC_E_6_THC0_SPI1_RSTB

GPPC_E_17_THC0_SPI1_INTB

GPPC_E_8_SPI1_CS1B_SATA_LEDB

GPPC_E_10_SPI1_CSB_THC0_SPI1_CSB

GPPC_E_13_SPI1_MOSI_IO_0_THC0_SPI1_IO_0

GPPC_E_12_SPI1_MISO_IO_1_THC0_SPI1_IO_1

GPPC_E_1_SPI1_IO_2_THC0_SPI1_IO_2

GPPC_E_2_SPI1_IO_3_THC0_SPI1_IO_3

GPPC_E_11_SPI1_CLK_THC0_SPI1_CLK

SPI0_TPM_CSB

SPI0_FLASH_0_CSB

SPI0_FLASH_1_CSB

SPI0_MOSI_IO_0

SPI0_MISO_IO_1

SPI0_IO_2

SPI0_IO_3

SPI0_CLK

OUT

OUT

BI

SPARE0

SPARE1

SPARE2

SPARE3

OUT

IN

OUT

IN

BI

BI

BI

BI

OUT

BI

BI

BI

BI

IN

BI
BI
BI
BI

BI

BI

BI

OUT

IN

T_POINT1

OUT

OUT

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

OUT

BI

BI

BI

BI

BI

OUT

OUT

BI
BI

 

 

TO IMVP

CPU :I2C/UART/SPI

PLACE RA CLOSE TO PCH,WITHIN 25.4MM

RA

B2B

GPPC_RCOMP MAIN ROUTE TRACE SPACING 100UM

UART HDR

B2B

B2B

B2B

UART HDR

TO LVDS

CR-11 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE11

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 11 OF 80

INTEL CONFIDENTIAL
<>

1

TP6R4

1

TP6R2

2

1

R4G9

2

1

R4G7

2

1

R4F3

DG17
DG19

DN33
DT35

DR51

DF25
DF27

DF29

DG29

DJ29
DJ31

DJ8
DR7
DR24
DU25

DV25
DT25

DR27
DW27

DV31
DU31
DT27
DV27

DJ19

DF21

DJ21

DG23

DJ23

DT18

DV18

DW18

DR18
DU19

DV19

DT19

DR21

DW21

DV21

DT21

CY53
CY52

CY49

DA50

DA51

DC49

DC53

DC52

DC50

DD47
DD44

CY39
DB47

DB45
DB44

U5E1

48D1 
48B8 

50C8 

76B7 

72D4 
72D4 

63B3 

63A2 

63A2 

63B3 

44B6 

60C7 

64B8 

64B8 

28B7 

48A4 

28C7 

64B8 

64C3 

64C3 
64C3 

64C3 

63B1 

63A4 

63A4 

63B1 

63A1 

63A4 

63A1 

63A4 

63A2 

63A3 

63A3 

63A2 

64A2 

64B3 

64A2 

64B3 

64A4 

64B3 

64A4 

64B3 

47A5 

47A5 

47A4 

46A8 

48D1 

48C1 

64B8 

TGL_U_IP

BMAP_REV=1.2

SOC

LPID6529

6 OF 21

1%

200

CH

1/16W

0402LF

1%

CH

15

0201LF

GPPC_D1_KEYB_FCP_OFF

GPPC_RCOMP

GPPC_D0_KEYB_RST

GPPC_E16_LAN_WAKE_N

GPPC_B8_V3P3_LAN_EN

GPPC_B10_I2C5_SCL
GPPC_B9_I2C5_SDA

UART2_TXD
UART2_RXD

GPPC_D18_LVDS_IRQ

GPPC_E15_ESPI_ALERT

GPPC_T2_DEBUG

GPPC_T3_DEBUG

GPPC_B22_SPI1_MOSI_R

CPU : I2C/UART/SPI

GPPC_B20_SPI1_CLK_R

GPPC_B18_SPI0_MOSI
GPPC_B17_SPI0_MISO
GPPC_B14_SPI0_CS1

GPPC_B20_SPI1_CLK
GPPC_B22_SPI1_MOSI
GPPC_B21_SPI1_MISO

UART0_TXD
UART0_RXD
UART0_CTS
UART0_RTS

UART1_TXD
UART1_RXD
UART1_CTS
UART1_RTS

UART2_CTS
UART2_RTS

I2C2_SCL
I2C2_SDA

I2C3_SCL
I2C3_SDA

CNV_MFUART2_TXD
CNV_MFUART2_RXD

GPPC_D14_KEYE_RST

GPPC_D13_KEYE_WAKE

GPPC_D15_KEYB_DISABLE_N

GPPC_D16_KEYB_WAKE_N

GPPC_B19_SPI1_CS0

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE: 

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

OUT

IN

BI

OUT

OUT

OUT

OUT

IN

OUT

IN

BI

BI

BI

IN

IN

IN

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

GPPC_U_4_GSPI3_CS0B

GPPC_U_5_GSPI3_CLK

GPPC_T_2_I2C7_SDA_FUSA_DIAGTEST_EN

GPPC_T_3_I2C7_SCL_FUSA_DIAGTEST_MODE

GPPC_RCOMP

GPPC_D_0_ISH_GP_0_BK_0_CAS_GP_0_SBK_0

GPPC_D_1_ISH_GP_1_BK_1_CAS_GP_1_SBK_1

GPPC_D_2_ISH_GP_2_BK_2_CAS_GP_2_SBK_2

GPPC_D_3_ISH_GP_3_BK_3_CAS_GP_3_SBK_3

GPPC_D_17_ISH_GP_4_CAS_GP_4

GPPC_D_18_ISH_GP_5_CAS_GP_5

GPPC_E_15_ISH_GP_6

GPPC_E_16_ISH_GP_7

GPPC_B_9_I2C5_SDA_ISH_I2C2_SDA_CAS_I2C2_SDA

GPPC_B_10_I2C5_SCL_ISH_I2C2_SCL_CAS_I2C2_SCL

GPPC_B_7_ISH_I2C1_SDA_CAS_I2C1_SDA

GPPC_B_8_ISH_I2C1_SCL_CAS_I2C1_SCL

GPPC_B_5_ISH_I2C0_SDA_CAS_I2C0_SDA

GPPC_B_6_ISH_I2C0_SCL_CAS_I2C0_SCL

GPPC_D_15_ISH_UART0_RTSB_GSPI2_CS1B_IMGCLKOUT_5

GPPC_D_16_ISH_UART0_CTSB_SML0BALERTB_CAS_SPIM_CS1B

GPPC_D_13_ISH_UART0_RXD_SML0BDATA_I2C4B_SDA

GPPC_D_14_ISH_UART0_TXD_SML0BCLK_I2C4B_SCL

GPPC_H_8_I2C4_SDA_CNV_MFUART2_RXD

GPPC_H_9_I2C4_SCL_CNV_MFUART2_TXD

GPPC_H_6_I2C3_SDA

GPPC_H_7_I2C3_SCL

GPPC_H_4_I2C2_SDA

GPPC_H_5_I2C2_SCL

GPPC_C_18_I2C1_SDA

GPPC_C_19_I2C1_SCL

GPPC_C_16_I2C0_SDA

GPPC_C_17_I2C0_SCL

GPPC_C_22_UART2_RTSB_CNV_MFUART0_RTS_B

GPPC_C_23_UART2_CTSB_CNV_MFUART0_CTS_B

GPPC_C_20_UART2_RXD_CNV_MFUART0_RXD

GPPC_C_21_UART2_TXD_CNV_MFUART0_TXD

GPPC_C_14_UART1_RTSB_ISH_UART1_RTSB

GPPC_C_15_UART1_CTSB_ISH_UART1_CTSB

GPPC_C_12_UART1_RXD_ISH_UART1_RXD

GPPC_C_13_UART1_TXD_ISH_UART1_TXD

GPPC_C_10_UART0_RTSB

GPPC_C_11_UART0_CTSB

GPPC_C_8_UART0_RXD

GPPC_C_9_UART0_TXD

GPPC_B_19_GSPI1_CS0B

GPPC_B_21_GSPI1_MISO_NFC_CLKREQ

GPPC_B_22_GSPI1_MOSI

GPPC_B_20_GSPI1_CLK_NFC_CLK

GPPC_B_15_GSPI0_CS0B

GPPC_B_14_SPKR_TIME_SYNC_1_GSPI0_CS1B

GPPC_B_17_GSPI0_MISO

GPPC_B_18_GSPI0_MOSI

GPPC_B_16_GSPI0_CLK

BI

IN

OUT

OUT

IN

IN

OUT

BI

OUT

BI

IN

OUT

 

 

M.2 KEYB

SLAVE MODE : 13 OHMS

MASTER MODE : 33 OHMS

ALL SGMII* SIGNALS ARE ON 1.8V DOMAIN

I2S1 SERIES RES

RA
1.8V : 0 OHMS

PLACE RA RES CLOSE TO MCP

RA

TO STRAPPING

3.3V : 33 OHMS

I2S MODE

SNDW_RCOMP MAIN ROUTE TRACE SPACING 380UM

I2S TO M.2 KEYE

PLACE 75K OHM RESISTORS CLOSE TO MCP

PLACE 33 OHM RESISTORS CLOSE TO MCP

CPU : AUDIO HDA

I2S TO

PCIE4_RCOMP/N MAIN ROUTE TRACE SPACING 380UM

BT_KILL

WIFI_KILL

PLACE 33 OHM RESISTORS CLOSE TO MCP

I2S2 SERIES RES

CR-12 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE12

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 12 OF 80

INTEL CONFIDENTIAL
<>

2

1

R4G5

2

1

R6R4

2

1

R8R6

2

1

C6R5

2

1

C6R1

2

1

R6R2

11

1

12

6

7

8

9

10

5

4

3

2

U7R1

2

1

R7R19

2

1

R3E21

2

1

R3E19

2

1

R3E20

2

1

R4P11

2

1

R3E11

2

1

R3E4

2

1

R3E15

2

1

R3E14

2

1

R6R5

DF33

DW15
DW24

DG41

DH49

DL52

DG50

DL49

DG51

DL53

DM31

DN31

DK31

DK33

DV35

DW35

DR35

DT32

DT38

DV38

DW38

DV41

DV37

DT37

DU37

DR38

U5E1

P5

T5

V5

Y5

P7

T7

V7

Y7

N1

R1

T1

V1

N2

R2

T2

V2

Y12
V12

U5E1

2

1

R4G6

2

1

R4G3

2

1

R4G2

2

1

R4G4

51B4  12C8 

12C8 

12C8 

52A8 

51B1 

12B1 

12B1 

12B1 
12B1 

51B4 

12D8 

51B1 
51B4 

12D1 

58A6 
12A8 

58B7 

47C4 

12A8 

12A8 

12A8 

58B3 

12C1 

12D1 

46D2 

12D1 

46C2 

46C2 

46D2 

12C8 

48C2 

12D8 

47B4 

64B8 
64B8 

48C2 

64B8 

64B8 

12B8 
12B8 

12B8 

48C2 

12D8 

58B6 
58B6 

12B8 

12D8 

48C2 

30C5 

V1P8_A

V3P3_A

V1P8_A

0402LF CH

33 5%

0402LF CH

33 5%

5%

CH

0402LF

33

0402LF

33 5%

CH

LPID6529

8 OF 21

TGL_U_IP

BMAP_REV=1.2

SOC

SOC

7 OF 21

TGL_U_IP

BMAP_REV=1.2

LPID6529

0402LF

1%
CH

200

1/16W

0402LF

5%

33

CH

RESN

1%

0402LF

2.2K

33

0402LF

5%

CH

0402LF CH

33 5%

CH

5%

33

0402LF

CH

0402LF

33 5%

IC

0402LF

10K 5%

CH

6.3V

X5R

0.1UF

10%

0201LF

0.1UF

10%

X5R

0201LF

6.3V

CH

1%

0402LF
1/16W

75K

0201LF

EMPTY

1/20W

100K
5%

CH

0402LF

1%

75K

GPP_S1_SGMII_INT

GPP_S0_SGMII_AUXTS

GPP_S2_SGMII_RST_N

SGMII_RST_N
SGMII_PPS

GPP_S3_SGMII_PPS

GPP_S2_SGMII_RST_N

GPP_S0_SGMII_AUXTS
GPP_S1_SGMII_INT

GPPC_R6_I2S1_TXD

SGMII_AUXTS
SGMII_INT

GPPC_A8_I2S2_RST_N

GPP_R4_HDA_RST_N_R

GPP_R4_HDA_RST_N

GPPC_A7_I2S2_SCLK

GPP_R0_HDA_BCLK_R

GPPC_A13_KEYE_BTKILL

GPPC_A9_I2S2_TXD

GPPC_A10_I2S2_RXD

GPPC_A8_I2S2_RST_N

GPP_R3_HDA_SDI

GPPC_A9_I2S2_TXD

GPPC_A10_I2S2_RXD

KEYE_BT_PCMFRM_CRF_RST_N

GPPC_A7_I2S2_SCLK

KEYE_BT_PCMIN

KEYE_BT_PCMOUT_CLKREQ

KEYE_BT_PCMCLK

GPP_S3_SGMII_PPS

PCIE4_COM0_RCOMP_N

PCIE4_COM0_RCOMP_P

KEYB_I2S1_SFRM

GPPC_A23_I2S1_SCLK

GPPC_A11

PCIE4_0_TX_DP
PCIE4_0_TX_DN

GPP_R0_HDA_BCLK

KEYB_I2S1_TXD

LVL_OE

PCIE4_0_RX_DN

PCIE4_0_RX_DP

GPPC_A23_I2S1_SCLK
GPPC_R7_I2S1_SFRM

GPPC_R5_I2S1_RXD

KEYB_I2S1_RXD

GPPC_R5_I2S1_RXD

GPP_R1_HDA_SYNC_R

GPP_R2_HDA_SDO_R

GPPC_R6_I2S1_TXD

GPPC_R7_I2S1_SFRM

KEYB_I2S1_SCLK

SNDW_RCOMP

GPP_R1_HDA_SYNC

GPP_R2_HDA_SDO

CPU : AUDIO HDA/I2S

CAD NOTE:

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE: 

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

CAD NOTE:

DESIGN NOTE:

CAD NOTE:

DESIGN NOTE:

DESIGN NOTE:

OUT

OUT

IN

OUT

IN

IN

OUT

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

TXB0104RUTR

A4

VCCB

B1

B2

B3

B4

OE

GND

A3

A2

A1

VCCA

OUT
OUT

IN

OUT

IN

IN

OUT

IN

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

OUT

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

IN
IN

OUT

IN

PCIE4_COM0_RCOMP_N

PCIE4_COM0_RCOMP_P

PCIE4_RX_N_0

PCIE4_RX_P_0

PCIE4_TX_N_0

PCIE4_TX_P_0

PCIE4_RX_P_1

PCIE4_RX_N_1

PCIE4_TX_N_1

PCIE4_TX_P_1

PCIE4_RX_N_2

PCIE4_RX_P_2

PCIE4_TX_N_2

PCIE4_TX_P_2

PCIE4_RX_N_3

PCIE4_RX_P_3

PCIE4_TX_N_3

PCIE4_TX_P_3

SNDW_RCOMP

GPPC_A_13_PMC_I2C_SCL_I2S3_TXD_DMIC_CLK_B_0

GPPC_A_11_PMC_I2C_SDA_I2S3_SCLK

GPPC_A_9_I2S2_TXD_MODEM_CLKREQ_CRF_XTAL_CLKREQ_DMIC_CLK_A_1

GPPC_A_10_I2S2_RXD_DMIC_DATA_1

GPPC_A_8_I2S2_SFRM_CNV_RF_RESET_B_DMIC_DATA_0

GPPC_A_7_I2S2_SCLK_DMIC_CLK_A_0

GPP_R_4_HDA_RSTB

GPP_R_3_HDA_SDI_0_I2S0_RXD_HDACPU_SDI

GPP_R_2_HDA_SDO_I2S0_TXD_HDACPU_SDO

GPP_R_1_HDA_SYNC_I2S0_SFRM

GPP_R_0_HDA_BCLK_I2S0_SCLK_HDACPU_BCLK

GPP_S_1_SNDW0_DATA_RGMII_INT

GPP_S_0_SNDW0_CLK_RGMII_AUXTS

GPP_S_3_SNDW1_DATA_DMIC_CLK_B_1_RGMII_PPS

GPP_S_2_SNDW1_CLK_DMIC_CLK_B_0_RGMII_RESET

GPP_S_5_SNDW2_DATA_DMIC_DATA_1

GPP_S_4_SNDW2_CLK_DMIC_CLK_A_1

GPP_S_7_SNDW3_DATA_DMIC_DATA_0

GPP_S_6_SNDW3_CLK_DMIC_CLK_A_0

GPP_R_5_HDA_SDI_1_I2S1_RXD

GPP_R_6_I2S1_TXD

GPP_R_7_I2S1_SFRM

GPPC_A_23_I2S1_SCLK

GPPC_D_19_I2S_MCLK1_OUT

GPPC_F_8_I2S_MCLK2_INOUT

 

 

2. ADVICE TO DEPOPULATE RA IF USING WWAN M.2 CARD  

1. SATAGP1 HAVE INTERNAL PU.

RA

USB2_1

PCIE_RCOMP/N MAIN ROUTE TRACE SPACING 200UM

CPU : PCIE / USB / SATA

GEN 2

GEN 2

USB3_3

USB2_2

USB2_3

USB2.0 MAIN ROUTE TRACE SPACING 200UM

ESATA/B2B

SATA 0

M.2 KEYB

PHY

B2B

B2B

KEY B

USB3_1

USB3_2

M.2 KEY B

KEY E

B2B

TRIPAD

USB2_4

M.2 KEY E

GBE

USB3_4

CR-13 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE13

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 13 OF 80

INTEL CONFIDENTIAL
<>

2

1

R7T1

2

1

R1J1

2

1

R1H4

2

1

R1J3

2

1

R1J5

2

1

R1H5

2

1

R1J4

2

1

R1J2

2

1

R1J6

2

1

R6P11

2

1

R4C5

2

1

R4C2

2

1

R4D1

CV4

DD5

CW9

DD1

DA1

DA12

DC8

DB4

DA5

DC11

CY3

DD4

DA9

DD2

DA2

DA11

DC7

DB3

DA4

DC9

DC12
DF1
DE1

E3

BT7
BT8

CE2
CE1

BT9

BV9
CF4
CF3

BV7
BV8

CG2
CG1

BY7
BY8

CG5
CG4

CB8
CB7
CK5
CK4

CD9
CD8

CK1
CK2

CG8
CG7

CL4
CL3

CJ8
CJ7

CN2
CN1

CR8
CR7
CN5
CN4

CU8
CU7

CT2
CT1

CW8
CW7

CU3

CT4

DA8
DA7
CV2
CV1

DV9
DT9

DN29
DK29
DT31
DR32

DD8

DN6
DG8

DP4

DJ45

DF41

U5E1

48D8 

64B3 

64C8 

48C8 

56A4 

55A4 

56A4 

55A4 

50C8 

50D8 

46B8 

48C8 

55B4 

46B7 

46B7 

46B8 

50D8 

50D8 

51D4 

48A6  48B6 

64B3 

13C7 

13C7 

57A2 

13C7 

64C8 

57A2 

64C8 

57A2 

64C8 

57A2 

48C6 

48C6 

54B8 

56C1 

54A4 

13C7 

57C6 

55C8 

54C4 

57C6 

57C6 

64C8 

64B8 

48C8 

55B4 

55B8 

54B4 

54B4 

54B8 

56D1 

54A4 

56D4 

54A4 

57C6 

56C4 

54A4 

64C8 

56A1 

55A4 

55B8 

56A1 

55A4 

51D8 

55C8 

48C8 

46D8 

46D8 

64B3 
64B3 

55C4 
55C4 

48C8 

48C6 

48C6 

13A8 

13A8 

13A8 

13A8 

51D8 

51D4 

64C8 

54C4 

54C8 

54C8 

56A5 

29C8  56D5 

LPID6529

BMAP_REV=1.2

TGL_U_IP

9 OF 21

SOC

CH

100 1%

0402LF

113
1%

1/16W

CH
0402LF

CH

1%

10K

1/16W

0402LF

1/16W

0402LF

1%
CH

10K

CH

0 5%

0402LF

5%

0402LF CH

0

PCIE_RCOMP_P
PCIE_RCOMP_N

USB2_ID

USB2_P6_DP

USB2_P8_DP

PCIE3_P9_RX_DP

PCIE3_P12_TX_DP

USB3_P3_RX_DN

USB3_P3_RX_DP

PCIE3_P7_RX_DN

PCIE3_P7_RX_DP

PCIE3_P6_TX_DP

PCIE3_P5_TX_DP

USB3_P4_TX_DN

PCIE3_P6_RX_DN

PCIE3_P6_RX_DP

PCIE3_P6_TX_DN

PCIE3_P7_TX_DN

PCIE3_P7_TX_DP

SGMII_0B_RXN

KEYB_WWAN_CONFIG1

USB2_P8_DN

PCIE3_P9_ESATA_TX_DN

PCIE3_P9_ESATA_RX_DP

ESATA_TX_DN

PCIE3_P9_ESATA_RX_DN

PCIE3_P9_TX_DP

ESATA_TX_DP

PCIE3_P9_TX_DN

ESATA_RX_DP

PCIE3_P9_RX_DN

ESATA_RX_DN

PCIE3_P5_RX_DP
PCIE3_P5_RX_DN

USB3_P1_TX_DP

USB3_P2_RX_DN

PCIE3_P9_ESATA_TX_DP

SATA0_RX_DN

USB2_P3_DN

USB2_P2_DP

SATA0_TX_DN
SATA0_RX_DP

PCIE3_P10_TX_DN

PCIE3_P10_RX_DN

PCIE3_P5_TX_DN

USB3_P4_TX_DP

USB3_P3_TX_DN

USB3_P2_TX_DN

USB3_P2_TX_DP

USB3_P1_TX_DN

USB3_P2_RX_DP

USB3_P1_RX_DP

SATA0_TX_DP

USB3_P1_RX_DN

PCIE3_P10_TX_DP

CPU : PCIE/USB/SATA

USB3_P4_RX_DN

USB3_P3_TX_DP

USB3_P4_RX_DP

SGMII_0B_TXP

USB2_P3_DP

USB2_P6_DN

USB2_P10_DN

USB2_P10_DP

USB2_P7_DP
USB2_P7_DN

USB2_P4_DP
USB2_P4_DN

PCIE3_P12_TX_DN
PCIE3_P12_RX_DP
PCIE3_P12_RX_DN

PCIE3_P9_ESATA_TX_DN
PCIE3_P9_ESATA_RX_DP
PCIE3_P9_ESATA_RX_DN

PCIE3_P9_ESATA_TX_DP

SGMII_0B_TXN
SGMII_0B_RXP

PCIE3_P10_RX_DP

USB2_P2_DN

USB2_P1_DN

USB2_P1_DP

SATA_PCIE_SELECTION

GPPC_A16_USB2_OC3_N

USB2_RCOMP

USB2_VBUS_SENSE

GPPC_E9_USB2_OC0_N

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE: 

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

CAD NOTE:

CAD NOTE:

DESIGN NOTE:

UFS_RESETB

USB2_COMP

USB2_ID

USB2_VBUSSENSE

MPHY_RCOMPN

MPHY_RCOMPP

GPPC_H_12_M2_SKT2_CFG_0

GPPC_H_13_M2_SKT2_CFG_1

GPPC_H_14_M2_SKT2_CFG_2

GPPC_H_15_M2_SKT2_CFG_3

GPPC_E_4_SATA_DEVSLP_0

GPPC_E_5_SATA_DEVSLP_1

GPPC_A_16_USB2_OCB_3_I2S4_SFRM

GPPC_E_9_USB2_OCB_0

GPPC_A_12_SATAXPCIE_1_SATAGP_1_I2S3_SFRM

GPPC_E_0_SATAXPCIE_0_SATAGP_0

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5

USB2P_5

USB2N_6

USB2P_6

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9

USB2N_10

USB2P_10

PCIE_1_USB31_1_RXN

PCIE_1_USB31_1_RXP

PCIE_1_USB31_1_TXN

PCIE_1_USB31_1_TXP

PCIE_2_USB31_2_RXN

PCIE_2_USB31_2_RXP

PCIE_2_USB31_2_TXN

PCIE_2_USB31_2_TXP

PCIE_3_USB31_3_RXN

PCIE_3_USB31_3_RXP

PCIE_3_USB31_3_TXN

PCIE_3_USB31_3_TXP

PCIE_4_USB31_4_RXN

PCIE_4_USB31_4_RXP

PCIE_4_USB31_4_TXN

PCIE_4_USB31_4_TXP

PCIE_5_RXN

PCIE_5_RXP

PCIE_5_TXN

PCIE_5_TXP

PCIE_6_RXN

PCIE_6_RXP

PCIE_6_TXN

PCIE_6_TXP

PCIE_7_UFS_00_LAN_0A_TSN_0A_RXN

PCIE_7_UFS_00_LAN_0A_TSN_0A_RXP

PCIE_7_UFS_00_LAN_0A_TSN_0A_TXN

PCIE_7_UFS_00_LAN_0A_TSN_0A_TXP

PCIE_8_UFS_01_LAN_0B_TSN_0B_RXN

PCIE_8_UFS_01_LAN_0B_TSN_0B_RXP

PCIE_8_UFS_01_LAN_0B_TSN_0B_TXN

PCIE_8_UFS_01_LAN_0B_TSN_0B_TXP

PCIE_9_UFS_10_LAN_0C_RXN

PCIE_9_UFS_10_LAN_0C_RXP

PCIE_9_UFS_10_LAN_0C_TXN

PCIE_9_UFS_10_LAN_0C_TXP

PCIE_10_UFS_11_RXN

PCIE_10_UFS_11_RXP

PCIE_10_UFS_11_TXN

PCIE_10_UFS_11_TXP

PCIE_11_SATA_0_TSN_0C_RXN

PCIE_11_SATA_0_TSN_0C_RXP

PCIE_11_SATA_0_TSN_0C_TXN

PCIE_11_SATA_0_TSN_0C_TXP

PCIE_12_SATA_1_TSN_0D_RXN

PCIE_12_SATA_1_TSN_0D_RXP

PCIE_12_SATA_1_TSN_0D_TXN

PCIE_12_SATA_1_TSN_0D_TXP

IN

BI

BI

IN
IN

OUT
OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

OUT

IN

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI

BI

BI

BI

IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

OUT
OUT

IN
IN

IN
IN

OUT
OUT

IN
IN

 

 

RA

CPU : CNV / CSI

CNV_WT_RCOMP MAIN ROUTE TRACE SPACING 200UM

CSI_RCOMP MAIN ROUTE TRACE SPACING 380UM

PLACE RA CLOSE TO PCH

CR-14 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE14

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 14 OF 80

INTEL CONFIDENTIAL
<>

2

1

R4P14

2

1

R7P1

2

1

R6P15

2

1

R6T5

DK25

DM25

DN25

DJ25

DV15

DJ10

DK10

DJ13
DG13
DF15
DF17

DR30

K14

D22

B22
E22

D20

A20
B20

B18
A18

D18

E18

C16
D16

D15

E15
A15
B15

L18

N18

L20

N20

G20

H20

H16

G16
G18

H18

L16

N16

G14

H14

L14

N14

DN51

DK47
DM47
DN49
DR49
DN45
DN47

DU43
DV43
DR44
DT43
DV44
DW44

U5E1

47B5 

14C3 

29A2 

14B4  29A7 

46B2 

46C1 

46A7 

46C1 

46B1 

29A2  14B4 

46A7 

46A7 

46A7 
46A7 
46A7 

46D6 
46C6 
46C6 
46C6 

46D6 

46C6 

14B3 

29A7 

LPID6529

10 OF 21

SOC

TGL_U_IP

BMAP_REV=1.2

150

CH

1/16W

0402LF

1%

5%

0

0 5%

1%

0402LF

CH

1/16W

150

CNV_PA_BLANKING

GPPC_F2_CNV_RGI_DT

GPPC_F0_CNV_BRI_DT

KEYE_CNV_BRI_DT

KEYE_CNV_RGI_DT

CNV_WT_D1_DP

GPPC_F1_CNV_BRI_RSP

GPPC_F3_CNV_RGI_RSP

GPPC_F2_CNV_RGI_DT

CSI_RCOMP

CNV_WT_D0_DP

CNV_WT_D1_DN

CPU : CNV/CSI

CNV_WT_D0_DN
CNV_WT_CLK_DP
CNV_WT_CLK_DN

CNV_WR_D1_DN
CNV_WR_D0_DP
CNV_WR_D0_DN
CNV_WR_CLK_DP

CNV_WR_D1_DP

CNV_WT_RCOMP

CNV_WR_CLK_DN

GPPC_F0_CNV_BRI_DT

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE: 

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

CAD NOTE:

CAD NOTE:

OUT

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN
IN

IN

IN

IN

GPPC_F_4_CNV_RF_RESET_B

GPPC_F_6_CNV_PA_BLANKING

GPPC_F_5_MODEM_CLKREQ_CRF_XTAL_CLKREQ

GPPC_F_0_CNV_BRI_DT_UART0_RTSB

GPPC_F_1_CNV_BRI_RSP_UART0_RXD

GPPC_F_2_CNV_RGI_DT_UART0_TXD

GPPC_F_3_CNV_RGI_RSP_UART0_CTSB

CNV_WT_RCOMP

CNV_WR_CLKN

CNV_WR_CLKP

CNV_WR_D0N

CNV_WR_D0P

CNV_WR_D1N

CNV_WR_D1P

CNV_WT_CLKN

CNV_WT_CLKP

CNV_WT_D0N

CNV_WT_D0P

CNV_WT_D1N

CNV_WT_D1P

GPPC_D_4_IMGCLKOUT_0_BK_4_SBK_4

GPPC_H_20_IMGCLKOUT_1

GPPC_H_21_IMGCLKOUT_2

GPPC_H_22_IMGCLKOUT_3

GPPC_H_23_IMGCLKOUT_4

CSI_RCOMP_1

CSI_A_D0N_B_D3N

CSI_A_D0P_B_D3P

CSI_A_D1N_B_D2N

CSI_A_D1P_B_D2P

CSI_B_CKN

CSI_B_CKP

CSI_B_D0N

CSI_B_D0P

CSI_B_D1N

CSI_B_D1P

CSI_C_CKN

CSI_C_CKP

CSI_C_D0N

CSI_C_D0P

CSI_C_D1N

CSI_C_D1P

CSI_D_D0N_C_D3N

CSI_D_D0P_C_D3P

CSI_D_D1N_C_D2N

CSI_D_D1P_C_D2P

CSI_E_CKN

CSI_E_CKP

CSI_E_D0N_F_D3N

CSI_E_D0P_F_D3P

CSI_E_D1N_F_D2N

CSI_E_D1P_F_D2P

CSI_F_CKN

CSI_F_CKP

CSI_F_D0N

CSI_F_D0P

CSI_F_D1N

CSI_F_D1P

 

 

JB

JA

SAVE CMOS - OPEN (DEFAULT)

CLEAR CMOS - SHORT

CLEAR ME RTC REGISTER - SHORT

SAVE ME  RTC REGISTER  - OPEN (DEFAULT)

JA - SRTC REST_N

JB - RTC REST_N

B2B

M.2 KEY B

B2B

GBE

B2B

GBE

B2B

KEY E

KEY B

CPU : PCIE CLOCK

TP

B2B

M.2 KEY E

CLK_BIASREF MAIN ROUTE TRACE SPACING 150UM TO GND

CR-15 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE15

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 15 OF 80

INTEL CONFIDENTIAL
<>

2

1

R4E1

1

TP6R3

2

1

R3D1

1

TP3D1

1

TP5C1

1

TP5C2

2

1

R4C3

2

1

R1E1

2

1

R1E2

2

1

R2N5

2

1

R8H5

2

1

R7T2

C2C7

R2C5

2

1

R2C2

2

1

R2C1

2

1

C2C6

R2C4

2

1

R7R6

2

1

R4C6

2

1

R4F2

2

1

C4C4

2

1

C4C1

2

1

C3F6

2

1

C3F5

2

4

3

1

Y3C1

2

1

Y3F1

DM1
DL1

DK37

DN37

DT47
DR47

DF23
DG25

DU14

DT24
DT30
DV30
DW30

DW41

BW1

CB2

BW4

CL7

CB4

BY4

CN7

BW2

CB1

BW5

CL8

CB5

BY3

CN8

DJ5

U5E1

64B8 

15C4 

46B7 

48C6 

15A5 

46B1 

64C8 
64C8 

50C7 

15A5 

50C7 

64B8 

64B8 

15C4 

64B8 

46B7 

48C6 

46B7 

48C2 

50C7 

64C8 

64C8 

V3P3A_RTC

V3P3_S

LPID6529

11 OF 21

SOC

TGL_U_IP

BMAP_REV=1.2

LPDB

XTAL

GENERIC

K38521-001

32.768KHZ

D71700-094

XTAL
38.4MHZ
+/-20PPM

GENERIC
LPDB

C0G

5%

18PF

25V

0201LF

5%

18PF

25V

0201LF

C0G

15PF

0201LF
50V

5%
C0G

5%
C0G

15PF

0201LF
50V

10M

CH

0402LF

5%

200K 1%

0402LF CH

1K

EMPTY

5%

0402LF
1/16W

0
0
EMPTY
0603LF
50V

6.3V

0402LF

X5R

1UF
20%

1%

20K

CH
0402LF
1/16W

0402LF

1%
CH

1/16W

20K

EMPTY

0

0

0603LF
50V

6.3V

20%
X5R

1UF

0402LF

10K

CH

1/16W

5%

0402LF

CH
0402LF

5%

10K

1/16W

5%

10K

CH

1/16W

0402LF

1/16W

CH

10K

0402LF

5%

10K

0402LF

5%
CH

1/16W

0402LF
1/16W

RESN

1%

60.4

TP

TP

TP

EMPTY

1/16W

0402LF

10K
5%

TP

10K
5%
EMPTY
0402LF
1/16W

CLK_BIASREF

PCIE4_CLK_DN

PCH_XTAL_OUT
PCH_XTAL_IN

SRTC_RST_N

RTC_XTAL_2

PCIE3_P1_CLK_DP

PCIE3_P2_CLK_DN

RTC_RST_N

SUS_CLK

RTC_XTAL_1

CLK_P0_REQ_N

PCIE3_P4_CLK_DP
PCIE3_P4_CLK_DN

PCIE3_P3_CLK_DP

SRTC_RST_N

PCIE3_P3_CLK_DN

PCIE3_P6_CLK_DN

PCIE3_P5_CLK_DN

PCIE3_P5_CLK_DP

RTC_RST_N

PCIE4_CLK_DP

PCIE3_P1_CLK_DN

PCIE3_P2_CLK_DP

PCIE3_P6_CLK_DP

CLK_P1_REQ_N

CLK_P2_REQ_N

CLK_P3_REQ_N

CLK_P4_REQ_N

CLK_P5_REQ_N

CLK_P6_REQ_N

CPU : PCIE CLOCK

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE: 

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

OUT
OUT

OUT

IN

IN

IN

IN

OUT

SRTCRSTB

RTESTB

RTCX1

RTCX2

GPD_8_SUSCLK

XTAL_IN

XTAL_OUT

GPPC_D_5_SRCCLKREQB_0

GPPC_D_6_SRCCLKREQB_1

GPPC_D_7_SRCCLKREQB_2

GPPC_D_8_SRCCLKREQB_3

GPPC_H_10_SRCCLKREQB_4

GPPC_H_11_SRCCLKREQB_5

GPPC_F_19_SRCCLKREQB_6

CLK_BIASREF

CLKOUT_SRC_N_0_G4

CLKOUT_SRC_P_0_G4

CLKOUT_SRC_N_1

CLKOUT_SRC_P_1

CLKOUT_SRC_N_2

CLKOUT_SRC_P_2

CLKOUT_SRC_N_3_G4

CLKOUT_SRC_P_3_G4

CLKOUT_SRC_N_4_UFS_REF_CLK_1

CLKOUT_SRC_P_4_UFS_REF_CLK_0

CLKOUT_SRC_N_5

CLKOUT_SRC_P_5

CLKOUT_SRC_N_6

CLKOUT_SRC_P_6

T_POINT1

T_POINT1

T_POINT1

T_POINT1

OUT
OUT

IN

OUT

OUT

OUT

OUT

IN

IN

OUT
OUT

OUT

OUT

OUT

 

 

PLACE RES CLOSE TO MCP WITHIN 1.5INCH

PLACE CLOSE TO MCP - WITHIN 100MILS

CPU : SYS PWR MANAGEMENT

CR-16 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE16

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 16 OF 80

INTEL CONFIDENTIAL
<>

1

TP6R10

4

5

3

2

1

U8W1

1

TP6R6

2

1

R4F1

1

TP6R12

2

1

R2J4

2

1

C2J1

2

1

R6R8

2

1

R6R12

1

TP6R11

2

1

R6R13

1

TP5P1

2

1

R5N8

2

1

R5N5

2

1

R6N4

2

1

R6N6

2

1

R6T2

R7R7

2

1

R6R11

2

1

R6R14

DK39

CE5
BP8
BP9

DD10

DF10

DT49

DV49

DN39

DM35

DN35

DM37

DN27
DG31

DW12

DR12

DD41

DD42

CW40

DT41

DM43

DT44

DN43

DR41

DJ41
DJ43

DK41

DM41

DK43

DN41

DK35

BM9

U5E1

30B2 

78B5 

78C1 

79C1 

78B6 

79C3 

79B5 

65B6 

79A5 

79B1 

38A4 

79B8 

64B3  79B5  39B7  40C5 
47A4  48A4  50C7  52A8 

57A7  60A8  63A7 

46A7  50C8  57A3 

57A3 

16A6 

16A4 

16A4 

77A8 

16C2 

50C7 

78C1 

29B8 

16B3 

16A3 

79A7 

40A3 

77A8 

16B8 

64B3 

79A7 

60B7 

65A1 

68A8 

69A7 

77C6 

79A4 

65A1 

79A5 

60B7 

66A8 

67C8 

79C8 

16C2 

16C2 

64B3  79B7  60B7  65A4  69A7  71A7  71B1  75A3  75A8  75C3 
75C8  77B8  78B2 

16C7 

78B5 

78C1 

16C7 

77D4 

16C2 

60A3 

60B7 

V3P3A_RTC

V3P3_A

VCCST_TERM

V3P3_A

12 OF 21

LPID6529

SOC

TGL_U_IP

BMAP_REV=1.2

1/16W

CH

10K
1%

0402LF

10K

1/16W

1%

0402LF

CH

CH

5%

0402LF

1M

1/16W

0

0

0402LF CH

CH

0 5%

0402LF

CH

5%

0

0402LF

1K
1%
CH
0402LF
1/16W

5%

62

0402LF CH

EMPTY

10K 1%

0402LF

0 5%

0402LF CH

5%

0

0402LF EMPTY

10%

0402LF

X5R

0.1UF

5%

0

0402LF EMPTY

1%

1K

CH

1/16W

0402LF

IC
C78568-001

TP

SPIVCCIOSEL

INTRUDER_N

PCH_PWROK

SYS_PWROK

DSW_PWROK

SYS_RST_N

PM_SLP_LAN_N

RSMRST_N

PM_PLTRST_N

PM_WAKE_N

GPPC_H3_DEBUG

CPUPWRGD

GPD2_LAN_WAKE_N

GPD_6_SLP_AB

VCCST_PWRGD
VCCST_OVERRIDE

VCCST_PWRGD_TCSS

CPU_C10_GATE_N

VCCST_OVERRIDE

GPD_11_LANPHYPC

SLG_PWRBTN_N

GPD7

ACPRESENT_N

BATLOW_N

PM_PWRBTN_N

PLTRST_N

PM_SLP_S0_N

SLP_WLAN_N

SLP_S3_N

PM_SLP_S4_N

PM_SLP_S5_N

PM_SLP_SUS_N

VCCST_PWRGD_TCSS

VCCST_PWRGD

PM_SLP_S3_N

SLP_S3_N

H_VCCST_PWRGD

PLTRST_N

VCCST_OVERRIDE_R

PM_PWRBTN_N

SLG_PWRBTN_SIO_OUT

CPU : SYS PWR MANAGEMENT

CAD NOTE:

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE: 

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

IN

IN

OUT

IN

IN

BI

OUT

IN

IN

OUT

IN

OUT

OUT

OUT

IN

OUT

OUT

OUT

IN

OUT

OUT

IN

OUT

IN

IN

IN

OUT

IN

OUT

T_POINT1

G

74AHC1G08

V

OUT

IN

OUT

OUT

IN

GPPC_F_21_EXT_PWR_GATE2B

GPPC_F_20_EXT_PWR_GATEB

VCCST_OVERRIDE

VCCST_PWRGD

VCCSTPWRGOOD_TCSS

GPD_7

GPD_11_LANPHYPC_DSWLDO_MON

GPD_2_LAN_WAKEB

WAKEB

GPPC_H_3_SX_EXIT_HOLDOFFB_IEH_FATAL_ERR2B

GPPC_H_18_CPU_C10_GATEB

GPPC_B_11_PMCALERTB

GPD_1_ACPRESENT

GPD_0_BATLOWB

GPD_3_PWRBTNB

CPUPWRGD

SPIVCCIOSEL

INTRUDERB

PCH_PWROK

SYS_PWROK

DSW_PWROK

GPPC_B_13_PLTRSTB

SYS_RESETB

RSMRSTB

SLP_LANB

GPPC_B_12_SLP_S0B

GPD_9_SLP_WLANB

GPD_6_SLP_AB

GPD_4_SLP_S3B

GPD_5_SLP_S4B

GPD_10_SLP_S5B

SLP_SUSB

 

 

PLACE THE RA CLOSE TO CPU

AND BREAKOUT AS 2 TRACES

AND BREAKOUT AS 2 TRACES

PLACE THE RA CLOSE TO CPU

RA

RB

RA

RA

CPU POWER : VCCIN

CPU

AND BREAKOUT AS 2 TRACES

PLACE THE RA CLOSE TO CPU

VR

RB

SVID

RB

CR-17 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE17

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 17 OF 80

INTEL CONFIDENTIAL
<>

2

1

R1T8

2

1

R4N10

2

1

R1T10

2

1

R4N13

2

1

R4N14

2

1

R9F11

2

1

R9F8

2

1

R4N8

2

1

R9F9

2

1

R4N12

2

1

R4N9

2

1

R1T9

R37

M12
M11
P12

R38

W32

W28

W24

W22

V33

V31

V29

V27

V25

V23

U33

U31

U29

U27

U23

T31

T27

T25

T23

T21

P32

P30

P28

P26

P24

N32

N30

N26

N24

L32

L30

L26

L24

K32

K30

K26

K24

K2

K1

J2

J1

H32

H30

H26

H24

G32

G30

G26

G24

G2

E33

E32

E30

E29

E27

E26

E24

D35

D33

D30

D29

D26

D24

CB12

CA10

BY12

BV12

BU40

BU10

BT39

BT12

BR40

BR10

BP39

BP12

BN40

BM39

BL40

BL10

BK39

BJ40

BJ10

BH9

BH39

BH12

BG40

BG10

BF9

BE40

BE10

BD9

BD39

BC40

BC10

BB9

BB39

BA40

BA10

B35

B33

B30

B29

B26

B24

AY39

A35

A33

A30

A29

A26

A24

U5E1

17A6 

72C1 

17B5 

17A5 

17C5 

72C1 

17A6 

17A6 

72C6 

72C6 

72B6 

VCCSTG_TERM

VCCIN

VCCIN

VCCSTG_TERM

VCCSTG_TERM

VCCSTG_TERM

VCCSTG_TERM

VCCSTG_TERM

LPID6529

13 OF 21

SOC

TGL_U_IP

BMAP_REV=1.2

1%

100

0402LF
1/16W

CH

0402LF
1/16W

1%

100

CH

CH

0 5%

0402LF

CH

0 5%

0402LF

CH

5%

0402LF
1/16W

56

CH

5%

0402LF

0

CH

0 5%

0402LF

0402LF

5%

CH

0

CH

0 5%

0402LF

5%

43

0402LF
1/16W

CH

5%

43

EMPTY

1/16W

0402LF

1/16W

110
1%
EMPTY
0402LF

VCCIN_VIDSOUT

VCC_VCCIN_SENSE_P

VR_SVID_CLK_R

PLACE THE RB CLOSE TO VR

PLACE THE RB CLOSE TO VR

CPU : VCCIN

VCCIN_VIDALERT_N

VCCIN_VIDSCK

VCCIN_VIDSOUT

VCC_VCCIN_SENSE_N

VCCIN_VIDSCK

VCCIN_VIDALERT_N

VR_SVID_DATA

VR_SVID_DATA_R

VR_SVID_CLK

PLACE THE RB CLOSE TO VR

VR_SVID_ALERT_R_N

VR_SVID_ALERT_N

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE: 

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

CAD NOTE:

CAD NOTE:

CAD NOTE:

CAD NOTE:

CAD NOTE:

BI

BI

VIDALERTB

VIDSCK

VIDSOUT

VSSIN_SENSE

VCCIN_SENSE

VCCIN_111

VCCIN_110

VCCIN_109

VCCIN_108

VCCIN_107

VCCIN_106

VCCIN_105

VCCIN_104

VCCIN_103

VCCIN_102

VCCIN_101

VCCIN_100

VCCIN_99

VCCIN_98

VCCIN_97

VCCIN_96

VCCIN_95

VCCIN_94

VCCIN_93

VCCIN_92

VCCIN_91

VCCIN_90

VCCIN_89

VCCIN_88

VCCIN_87

VCCIN_86

VCCIN_85

VCCIN_84

VCCIN_83

VCCIN_82

VCCIN_81

VCCIN_80

VCCIN_79

VCCIN_78

VCCIN_77

VCCIN_76

VCCIN_75

VCCIN_74

VCCIN_73

VCCIN_72

VCCIN_71

VCCIN_70

VCCIN_69

VCCIN_68

VCCIN_67

VCCIN_66

VCCIN_65

VCCIN_64

VCCIN_63

VCCIN_62

VCCIN_61

VCCIN_60

VCCIN_59

VCCIN_58

VCCIN_57

VCCIN_56

VCCIN_55

VCCIN_54

VCCIN_53

VCCIN_52

VCCIN_51

VCCIN_50

VCCIN_49

VCCIN_48

VCCIN_47

VCCIN_46

VCCIN_45

VCCIN_44

VCCIN_43

VCCIN_42

VCCIN_41

VCCIN_40

VCCIN_39

VCCIN_38

VCCIN_37

VCCIN_36

VCCIN_35

VCCIN_34

VCCIN_33

VCCIN_32

VCCIN_31

VCCIN_30

VCCIN_29

VCCIN_28

VCCIN_27

VCCIN_26

VCCIN_25

VCCIN_24

VCCIN_23

VCCIN_22

VCCIN_21

VCCIN_20

VCCIN_19

VCCIN_18

VCCIN_17

VCCIN_16

VCCIN_15

VCCIN_14

VCCIN_13

VCCIN_12

VCCIN_11

VCCIN_10

VCCIN_9

VCCIN_8

VCCIN_7

VCCIN_6

VCCIN_5

VCCIN_4

VCCIN_3

VCCIN_2

VCCIN_1

IN

OUT

OUT

OUT

OUT

BI

BI

BI

BI

 

 

CPU POWER: VDD2_MEM/VCCSTG/VCCST

CAD NOTE: CLOSE TO BGA

CR-18 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE18

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 18 OF 80

INTEL CONFIDENTIAL
<>

1

TP4P4

1

TP4P8

1

TP4P6

2

1

C4N1

2

1

C5N3

2

1

C4N6

2

1

C4N5

2

1

R5N4

2

1

R4N15

2

1

R4N21

2

1

R4N16

2

1

R5C5

AF12
AD12

M9

AF9

BP4

BP2
BP1

BT4

BT2
BT1

V15

AN10
AM9
AG10

T52

T51

F49

E51

D50

CR40

CP47

CN40

CL40

CJ40

CH39

CG40

CE40

CC50

CC49

CC40

CA40

BV52

BV51

BK52

BK51

BD52

BD51

AW52

AW51

AW40

AU40

AT52

AR39

AP40

AN39

AM40

AL39

AK52

AK51

AK40

AJ39

AH40

AG39

AF40

AE39

AD52

AD51

AD40

AC39

AB40

AA39

U5E1

VCCSTG_FUSE

VCCST

VCCSTG

VCCSTG_FUSE

VCCSTG

VCCSTG_FUSE

VCCSTG_OUT_FUSE

VCCFPGM

VCCST_TERM

VCCSTG_TERM

VCCST

VCCSTG_OUT_LGC

VDDQ_MEM

VCCSTG_OUT_LGC

VCCION_OUT

VCCFPGM

VCCSTG_OUT_FUSE

LPID6529

TGL_U_IP

BMAP_REV=1.2

15 OF 21

SOC

EMPTY

0

0603LF

0

CH

0603LF

0.01 1%

CH

0603LF

0.01 1%

CH

0603LF

0.01 1%

CH

0603LF

0.01 1%

10V

X5R
0201LF

1UF
20%

1UF

10V

0201LF

X5R

20%

10V

20%

1UF

0201LF

X5R

10V

20%

0201LF

X5R

1UF

TP

TP

TP

CPU : CPU POWER

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE: 

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

T_POINT1

T_POINT1

T_POINT1

VCCSTG_3

VCCSTG_1

VCCSTG_2

VCCST_3

VCCST_1

VCCST_2

VCCSTG_OUT_LGC

VCCION_OUT

VCCFPGM0

VCCFPGM1

VCCFPGM2

VCCSTGFUSE_1

VCCSTGFUSE_2

VCCSTG_OUT_FUSE

VCCDD2_47

VCCDD2_46

VCCDD2_45

VCCDD2_44

VCCDD2_43

VCCDD2_42

VCCDD2_41

VCCDD2_40

VCCDD2_39

VCCDD2_38

VCCDD2_37

VCCDD2_36

VCCDD2_35

VCCDD2_34

VCCDD2_33

VCCDD2_32

VCCDD2_31

VCCDD2_30

VCCDD2_29

VCCDD2_28

VCCDD2_27

VCCDD2_26

VCCDD2_25

VCCDD2_24

VCCDD2_23

VCCDD2_22

VCCDD2_21

VCCDD2_20

VCCDD2_19

VCCDD2_18

VCCDD2_17

VCCDD2_16

VCCDD2_15

VCCDD2_14

VCCDD2_13

VCCDD2_12

VCCDD2_11

VCCDD2_10

VCCDD2_9

VCCDD2_8

VCCDD2_7

VCCDD2_6

VCCDD2_5

VCCDD2_4

VCCDD2_3

VCCDD2_2

VCCDD2_1

 

 

CLOSE TO BGA

HDA: V3P3_A(DEFAULT)

AS PER PI FEEBACK

CAP ADDED FOR PI SIMULATION

DESIGN NOTE:

PCH POWER : VCCIN_AUX/VNN/1.05V/1.8V/3.3V

I2S: V1P8_A

CLOSE TO BGA

CLOSE VCCPRIM_1P8 PIN

CR-19 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE19

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 19 OF 80

INTEL CONFIDENTIAL
<>

2

1

L7P1

2

1

C6P9

2

1

C6P8

2

1

R7R1

2

1

R7P10

2

1

R6T8

2

1

R7R5

2

1

R6R7

2

1

R6R6

2

1

C5N5

2

1

C6R4

2

1

C7R4

2

1

C7R5

2

1

C6R6

2

1

C6R8

2

1

C7P1

2

1

R7P3

2

1

R7P4

2

1

R7R8

2

1

R7R2

2

1

C6R3

2

1

C6R2

2

1

C6P6

2

1

R6P14

2

1

R7P5

2

1

C4N4

2

1

R4N11

1

TP6R9

1

TP5N1

1

TP6R1

1

TP6R5

1

TP4P7

1

TP4F1

1

TP6R7

2

1

C4E2

2

1

C4E1

2

1

C6P5

2

1

C6P4

DV34

DC35

DC33
DC31

DD30

DC30

DC28

DA35

DV22

DD22

DD20

DC26

DC24

DC22

DC20

DC18

DA26

DA24

DA22

DA20

DA18

CY26

CY24

CY20

CY18

DA28

CY33

CY31

CV39

DD37

DV46

AK1

AV9

AT9

CY1

CU12

CT10

CR12

CP10

CP1

CM10

CL12

CK10

CJ12

CJ1

CH10

CG12

CF10

CD12

CC1

BY39

BW40

BV39

BV1

AW10

AU10

AT12

AR10

AK2

AE10

AC10

AB12

DD38

DV28

AP12

DV16
DC15

DD18

DD17

DA17

DA15

DA31

BT5

BR4

BR3

DT12

DV12

DB39

DB38

DB37

U5E1

0603LF X5R

0402LF CH

0 0

V1P8A_R

V1P05_OUT_FET

0603LF

VCCDSW_3P3

CH

VCCA_CLKLDO_1P8

10V

V1P8_A

X5R

20%
X5R
0201LF

0603LF

0 1A

EMPTY

30%

2.7A

J65894-001

47UF

VLDOSTD_OUT_0P85

0.68UH

VPHY_1P24

V1P8_A

V3P3_A

VPGPPR_1P8_3P3

0201LF

0

0

20%

V1P05_OUT_PCH

CPU : PCH POWER

1UF

10V

10V

X5R

20%

0201LF

VCCIN_AUX_VCCSENS

VNN_CTRL

VCCIN_AUX_VSSSENS

GPPC_B2_PROCHOT_N_R

X5R

VCCIN_AUX_CORE_VID1_R

VCCIN_AUX_CORE_VID0_R

VCCIN_AUX_CORE_VID1

VCCIN_AUX_CORE_VID0

V1P05_CTRL

GPPC_B2_PROCHOT_N

20%

1UF

0201LF

CH

0603LF

0 1A

EMPTY

0603LF

0 0

0

CH

5%

0402LF

CH

0402LF

0

CH

5%

0 5%

0402LF CH

X5R

20%

1UF

0201LF
10V

1UF
20%
X5R

10V

X5R

10%

0.1UF

0402LF

0201LF
10V

20%

1UF

X5R

0402LF

X5R

20%

6.3V

1A

0

0603LF CH

0603LF CH

1%

0.01

0201LF

X5R

10V

1UF
20%

10V

10%
X5R
0402LF

0.1UF

10V

0201LF

1UF

X5R

20%

1%
EMPTY
0402LF

100K

1/16W

1/16W

EMPTY

100K
1%

0402LF

0402LF

X5R

20%

10UF

6.3V

0603LF CH

1%

0.01

TP

TP

TP

TP

0402LF

X5R

0.1UF

6.3V

X5R

20%

4.7UF

SOC

14 OF 21

LPID6529

BMAP_REV=1.2

TGL_U_IP

VCCIN_AUX

VCCIN_AUX_FIL

VCCIN_AUX

VPHY_1P24

VNN_EXT

V1P05_EXT

V1P05_EXT

VNN_EXT

V3P3A_RTC

VCCIN_AUX_FIL

V3P3_A

VCCPFUSE_3P3

VDSW_1P05

V3P3A_RTC

V1P05_OUT_FET

VRTC_EXT

V1P8_A

V3P3_A

VPGPPR_1P8_3P3

VCCPFUSE_1P8

V1P8_A

22UF

VLDOSTD_OUT_0P85

V1P05_OUT_PCH

0402LF

10%

VDSW_1P05

10V

0201LF

X5R

20%

1UF

1UF

10V

20%

1UF

0201LF

V3P3_A

VCCDSW_3P3

V1P8_A

V1P8_A

10V

VCCPFUSE_1P8

70A1 

71A7 

70A1 

70B7  70A6 

70B7  70A8 

71C8 

22C8 

VRTC_EXT

V1P8_A

6.3V

V3P3_A

TP

VCCPFUSE_3P3

TP

TP

VCCANA_EHV

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE: 

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

DESIGN NOTE:

CAD NOTE:

CAD NOTE:

OUT

OUT

IN

VCCANA_EHV

VCCPFUSE_1P8

VCCPFUSE_3P3_2

VCCPFUSE_3P3_1

VCCPGPPR

VCCPDSW_3P3

VCCPRTC_3P3

VCCPRIM_CNVLDO_1P05

VCCPRIM_FUSE_1P05

VCC1P05_OUT_PCH

VCC1P05_OUT_FET_3

VCC1P05_OUT_FET_2

VCC1P05_OUT_FET_1

VCCDSW_1P05

VCCDPHY_1P24

VCCA_CLKLDO_1P8_1

VCCA_CLKLDO_1P8_2

VCCLDOSTD_OUT_0P85

VCCRTCEXT

VCCPRIM_3P3_4

VCCPRIM_3P3_3

VCCPRIM_3P3_2

VCCPRIM_3P3_1

VCCPRIM_1P8_17

VCCPRIM_1P8_16

VCCPRIM_1P8_15

VCCPRIM_1P8_14

VCCPRIM_1P8_13

VCCPRIM_1P8_12

VCCPRIM_1P8_11

VCCPRIM_1P8_10

VCCPRIM_1P8_9

VCCPRIM_1P8_8

VCCPRIM_1P8_7

VCCPRIM_1P8_6

VCCPRIM_1P8_5

VCCPRIM_1P8_4

VCCPRIM_1P8_3

VCCPRIM_1P8_2

VCCPRIM_1P8_1

GPPC_B_1_CORE_VID_1

GPPC_B_0_CORE_VID_0

GPPC_F_23_V1P05_CTRL_IEH_NONFATAL_ERR1B

GPPC_F_22_VNN_CTRL_IEH_CORR_ERR0B

GPPC_B_2_VRALERTB

VCC_V1P05EXT_1P05_2

VCC_V1P05EXT_1P05_1

VCC_VNNEXT_1P05_2

VCC_VNNEXT_1P05_1

VCCIN_AUX_VCCSENSE

VCCIN_AUX_VSSSENSE

VCCINAUX_FIL

VCCIN_AUX_28

VCCIN_AUX_27

VCCIN_AUX_26

VCCIN_AUX_25

VCCIN_AUX_24

VCCIN_AUX_23

VCCIN_AUX_22

VCCIN_AUX_21

VCCIN_AUX_20

VCCIN_AUX_19

VCCIN_AUX_18

VCCIN_AUX_17

VCCIN_AUX_16

VCCIN_AUX_15

VCCIN_AUX_14

VCCIN_AUX_13

VCCIN_AUX_12

VCCIN_AUX_11

VCCIN_AUX_10

VCCIN_AUX_9

VCCIN_AUX_8

VCCIN_AUX_7

VCCIN_AUX_6

VCCIN_AUX_5

VCCIN_AUX_4

VCCIN_AUX_3

VCCIN_AUX_2

VCCIN_AUX_1

OUT
OUT

OUT
OUT

T_POINT1

T_POINT1

T_POINT1

T_POINT1

T_POINT1

T_POINT1

T_POINT1

 

 

CPU : CORE GND

CR-20 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE20

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 20 OF 80

INTEL CONFIDENTIAL
<>

Y8

Y50

Y49

Y4

W48

W47

W45

W44

W42

W41

W39

W30

W26

W16

W1

V8

V4

V19

U49

U39

U25

U19

T8

T48

T4

T33

T29

T19

R44

R39

P8

P49

P4

P35

P33

P22

P20

P18

P16

P14

P11

N48

N41

N39

N34

N28

N22

M50

M2

M1

L49

L47

L45

L44

L42

L41

L39

L34

L28

L22

K5

K48

K34

K28

K22

K20

K18

K16

J49

J39

H8

H34

H28

H22

H12

G52

G51

G48

G39

G34

G28

G22

E48

E35

E19

E13

DW51

DV52

DV40

DV1

DU46

DU40

DU34

DU28

DU22

DU16

DU11

DT50

DT4

DR46

DR40

DR34

DR28

DR22

DR16

DR11

DP53

U5E1

DN2

DN1

DM45

DM4

DM39

DM33

DM27

DM21

DM15

DM10

DL5

DL3

DK51

DJ4

DJ2

DJ1

DG6

DG53

DG5

DG45

DG39

DG33

DG27

DG21

DG15

DF37

DF19

DE5

DE3

DD52

DD51

DD45

DD39

DD35

DD33

DD31

DD28

DD26

DD24

DD15

DC17

DA53

DA33

DA30

D5

D49

D42

D36

D32

D27

CY5

CY47

CY45

CY44

CY42

CY41

CY35

CY22

CY17

CV52

CV51

CV5

CV48

CV10

CU9

CU4

CT5

CR9

CR53

CR48

CP5

CP45

CP44

CP42

CP41

CP3

CN9

CN52

CN51

CN48

CN12

CL9

CK53

CK48

CK39

CJ9

CJ5

CJ3

CH47

CH45

CH44

CH42

CH41

CG9

CG52

CG51

CG48

CE49

CD7

CD48

CD44

CC5

CC3

CC10

CB41

CA48

C23

C19

C13

BY9

BY49

BY47

BY45

BY44

U5E1

BY42

BY41

BW10

BV5

BV48

BV3

BU49

BT48

BT44

BP7

BP50

BP5

BP49

BP41

BN48

BM8

BM47

BM45

BM44

BM42

BM41

BM4

BM1

BL49

BK8

BK48

BK4

BK12

BH8

BH4

BH2

BH1

BG53

BG48

BF8

BF7

BF5

BF47

BF45

BF44

BF42

BF41

BF4

BF39

BD8

BD48

BD4

BD12

BC2

BC1

BB8

BB4

BA53

BA48

B8

B52

B48

B42

B39

B36

B32

B27

B23

B2

B19

B13

AY9

AY8

AY47

AY45

AY44

AY42

AY41

AY4

AW48

AW2

AW1

AV8

AV7

AV5

AV4

AV39

AV12

AT8

AT51

AT48

AT4

AP8

AP4

AN53

AN48

AN47

AN45

AN44

AN42

AN41

AM8

AM4

AM2

AM1

AK8

AK7

AK5

AK48

AK4

AK12

AH8

AH4

AG53

AG48

AG47

AG45

AG44

AG42

AG41

AF8

AF4

AD8

AD48

AD4

AC49

AC44

AB8

AB7

AB5

AA48

AA41

A49

A45

A32

A27

U5E1

16 OF 21

SOC

TGL_U_IP

BMAP_REV=1.2

LPID6529

17 OF 21

SOC

TGL_U_IP

BMAP_REV=1.2

LPID6529

LPID6529

BMAP_REV=1.2

TGL_U_IP

SOC

18 OF 21

CPU : GND

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE: 

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

VSS_245

VSS_244

VSS_243

VSS_242

VSS_241

VSS_240

VSS_239

VSS_238

VSS_237

VSS_236

VSS_235

VSS_234

VSS_233

VSS_232

VSS_231

VSS_230

VSS_229

VSS_228

VSS_227

VSS_226

VSS_225

VSS_224

VSS_223

VSS_222

VSS_221

VSS_220

VSS_219

VSS_218

VSS_217

VSS_216

VSS_215

VSS_214

VSS_213

VSS_212

VSS_211

VSS_210

VSS_209

VSS_208

VSS_207

VSS_206

VSS_205

VSS_204

VSS_203

VSS_202

VSS_201

VSS_200

VSS_199

VSS_198

VSS_197

VSS_196

VSS_195

VSS_194

VSS_193

VSS_192

VSS_191

VSS_190

VSS_189

VSS_188

VSS_187

VSS_186

VSS_185

VSS_184

VSS_183

VSS_182

VSS_181

VSS_180

VSS_179

VSS_178

VSS_177

VSS_176

VSS_175

VSS_174

VSS_173

VSS_172

VSS_171

VSS_170

VSS_169

VSS_168

VSS_167

VSS_166

VSS_165

VSS_164

VSS_163

VSS_162

VSS_161

VSS_160

VSS_159

VSS_158

VSS_157

VSS_156

VSS_155

VSS_154

VSS_153

VSS_152

VSS_151

VSS_150

VSS_149

VSS_148

VSS_147

VSS_146

VSS_145

VSS_144

VSS_143

VSS_142

VSS_141

VSS_140

VSS_139

VSS_138

VSS_137

VSS_136

VSS_135

VSS_134

VSS_133

VSS_132

VSS_131

VSS_130

VSS_129

VSS_128

VSS_127

VSS_126

VSS_125

VSS_124

VSS_123

VSS_122

VSS_121

VSS_120

VSS_119

VSS_118

VSS_117

VSS_116

VSS_115

VSS_114

VSS_113

VSS_112

VSS_111

VSS_110

VSS_109

VSS_108

VSS_107

VSS_106

VSS_105

VSS_104

VSS_103

VSS_102

VSS_101

VSS_100

VSS_99

VSS_98

VSS_97

VSS_96

VSS_95

VSS_94

VSS_93

VSS_92

VSS_91

VSS_90

VSS_89

VSS_88

VSS_87

VSS_86

VSS_85

VSS_84

VSS_83

VSS_82

VSS_81

VSS_80

VSS_79

VSS_78

VSS_77

VSS_76

VSS_75

VSS_74

VSS_73

VSS_72

VSS_71

VSS_70

VSS_69

VSS_68

VSS_67

VSS_66

VSS_65

VSS_64

VSS_63

VSS_62

VSS_61

VSS_60

VSS_59

VSS_58

VSS_57

VSS_56

VSS_55

VSS_54

VSS_53

VSS_52

VSS_51

VSS_50

VSS_49

VSS_48

VSS_47

VSS_46

VSS_45

VSS_44

VSS_43

VSS_42

VSS_41

VSS_40

VSS_39

VSS_38

VSS_37

VSS_36

VSS_35

VSS_34

VSS_33

VSS_32

VSS_31

VSS_30

VSS_29

VSS_28

VSS_27

VSS_26

VSS_25

VSS_24

VSS_23

VSS_22

VSS_21

VSS_20

VSS_19

VSS_18

VSS_17

VSS_16

VSS_15

VSS_14

VSS_13

VSS_12

VSS_11

VSS_10

VSS_9

VSS_8

VSS_7

VSS_6

VSS_5

VSS_4

VSS_3

VSS_2

VSS_1

VSS_352

VSS_351

VSS_350

VSS_349

VSS_348

VSS_347

VSS_346

VSS_345

VSS_344

VSS_343

VSS_342

VSS_341

VSS_340

VSS_339

VSS_338

VSS_337

VSS_336

VSS_335

VSS_334

VSS_333

VSS_332

VSS_331

VSS_330

VSS_329

VSS_328

VSS_327

VSS_326

VSS_325

VSS_324

VSS_323

VSS_322

VSS_321

VSS_320

VSS_319

VSS_318

VSS_317

VSS_316

VSS_315

VSS_314

VSS_313

VSS_312

VSS_311

VSS_310

VSS_309

VSS_308

VSS_307

VSS_306

VSS_305

VSS_304

VSS_303

VSS_302

VSS_301

VSS_300

VSS_299

VSS_298

VSS_297

VSS_296

VSS_295

VSS_294

VSS_293

VSS_292

VSS_291

VSS_290

VSS_289

VSS_288

VSS_287

VSS_286

VSS_285

VSS_284

VSS_283

VSS_282

VSS_281

VSS_280

VSS_279

VSS_278

VSS_277

VSS_276

VSS_275

VSS_274

VSS_273

VSS_272

VSS_271

VSS_270

VSS_269

VSS_268

VSS_267

VSS_266

VSS_265

VSS_264

VSS_263

VSS_262

VSS_261

VSS_260

VSS_259

VSS_258

VSS_257

VSS_256

VSS_255

VSS_254

VSS_253

VSS_252

VSS_251

VSS_250

VSS_249

VSS_248

VSS_247

VSS_246

 

 

RVP: VSS_1

CPU : XDP / FIVR DEBUG

CR-21 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE21

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 21 OF 80

INTEL CONFIDENTIAL
<>

1

TP4P5

1

TP4P9

2

1

R7C2

DU1
DT2

DW5

BN10

W34

BM12

V35

DD13

DF13

AR2

AL10

AH12

AM12

AJ10

AR1

D52

DW2
DV2

C1
D2

E1
F1

DV4
DW3

DW6
DV6

T15

V17

U15

K11
K12

K9

T17

K7

H7

K8

H9

E6

H5

E9

D9

E7

B5

U17
H11

Y1

M4

AB4

Y2

A3
B3

DV51
DW52
DV53

A51
B51

AB2

CP39
CU40
AK9

AH9

DR53

DR1
DR2

U5E1

DF50
DF49

CY28

CY30
CY15

DF52

DF53

DT52

DU53

C53
T35
E53
CF39
U35
F53
B53
AP9
A52

BF12
V21
W20
U37
CD39
U21
CB39
BB12
W37
AY12
W38
U38

A6
A4

D4

U5E1

79A4 

26C6 
26D6 

26B6 

26B6 

26A6 

26D4 

26D3 

26C3 

26B3 

26B2 

26A2 

27C7 

27B7 

27A7 

27B4 

27A5 

19 OF 21

SOC

TGL_U_IP

BMAP_REV=1.2

LPID6529

BMAP_REV=1.2

TGL_U_IP

SOC

20 OF 21

LPID6529

CH

1%

0402LF

49.9

1/16W

TP
TP

NOA_STB_P_0

SKTOCC_N

NOA_RCOMP

CPU : XDP/FIVR DEBUG

NOA_STB_P_1

XDP_NOA1_N

XDP_NOA0_N

XDP_NOA2_N

XDP_NOA3_N

XDP_NOA4_N

XDP_NOA5_N

XDP_NOA6_N

XDP_NOA7_N

XDP_NOA8_N

XDP_NOA9_N

XDP_NOA10_N

XDP_NOA11_N

XDP_NOA12_N

XDP_NOA13_N

XDP_NOA14_N

XDP_NOA15_N

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE: 

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

SKTOCC_N

THERMDA

THERMDC

FPF_LDOMON

FPF_MON

FPF_VREF

USB2PLL_HPLDO_MON

CNVLDO_MON

CKPLL_MON*

CKPLL_MON_P

DDIA_OBS

PCIE4_COM0_DFX_DAMON_OBSN_LV

PCIE4_COM0_DFX_DAMON_OBSP_LV

SATA_PLLOBSN

SATA_PLLOBSP

USB31_PLLOBSN

USB31_PLLOBSP

PCIE3_PLLOBSN

PCIE3_PLLOBSP

PCH_EDM1

PCH_EDM2

CPU_EDM_0

CPU_EDM_1

CPU_POPIO_VIEW_0

CPU_POPIO_VIEW_1

PEG_VIEW2

PEG_VIEW3

DDR_VIEW_0

DDR_VIEW_1

TD_ANODE

TD_CATHODE

THERMDA_GT

THERMDC_GT

TCP0_DFX_AMON_OBS_LV

TCP0_DFX_DMONOBS_N_LV0

TCP0_DFX_DMONOBS_P_LV0

TCP0_DFX_DMONOBS_N_LV1

TCP0_DFX_DMONOBS_P_LV1

TCP0_DFX_RCOMP_OBS_LV

HVM_CLK*

HVM_CLK_P

MBPB_0

MBPB_1

MBPB_2

MBPB_3

NOA_AVRB_STB_P_0

NOA_AVRB_STB_P_1

NOA_RCOMP

NOAB_0

NOAB_1

NOAB_2

NOAB_3

NOAB_4

NOAB_5

NOAB_6

NOAB_7

NOAB_8

NOAB_9

NOAB_10

NOAB_11

NOAB_12

NOAB_13

NOAB_14

NOAB_15

OUT

T_POINT1

T_POINT1

OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT

PCHFIVR_VLOAD_VNNAON

FIVR_VLOAD_CCF

FIVR_VLOAD_CORE0

FIVR_VLOAD_CORE1

FIVR_VLOAD_CORE2

FIVR_VLOAD_CORE3

FIVR_VLOAD_GT

FIVR_VLOAD_SA

FIVR_VLOAD_VCCDDQ

FIVR_VLOAD_VCCIOE

FIVR_VLOAD_VCCION

FIVR_VLOAD_VCCPCIE

FIVR_VLOAD_VCCTCPHY

FIVR_VTARGET_CCF

FIVR_VTARGET_CORE

FIVR_VTARGET_GT

FIVR_VTARGET_PCIE

FIVR_VTARGET_SA

FIVR_VTARGET_TCSS

FIVR_VTARGET_VCCIOE

FIVR_VTARGET_VCCION

FIVR_VTARGET_VDDQ

FIVR_PROBE_ANA_0

FIVR_PROBE_ANA_1

EXTBGREF

PCHFIVR_VLOAD_1P05

PCHFIVR_VLOAD_VNN

PCHFIVR_VTARGET_1P05

PCHFIVR_VTARGET_VNN

PCHFIVR_ANAPB0

PCHFIVR_ANAPB1

PCHFIVR_REFCLK

PCHFIVR_EXTBGREF

 

 

NC

CPU : JTAG/MISC

PLACE CLOSE TO MCP

WITHIN 1 INCH

MAIN ROUTE TRACE SPACING 300UM

CPU_POPI_RCOMP & PCH_OPI_RCOMP

CPU+PCH JTAG TP

CR-22 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE22

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 22 OF 80

INTEL CONFIDENTIAL
<>

2

1

R5N7

2

1

R6T7

1

2

CR6T1

1

TP4P1

1

TP7D2

1

TP3P3

2

1

R3P7

2

1

R4N7

2

1

R5C4

2

1

R4N17

2

1

R7D6

2

1

R3P10

2

1

R7D3

2

1

R7D2

1

TP7C2

2

1

R7D5

2

1

R3P9

2

1

R3P13

2

1

R3P14

1

TP3P2

2

1

R3P8

2

1

R3P12

1

TP3P1

2

1

R3P15

2

1

R3P11

1

TP7C1

2

1

R7C1

2

1

R7C5

2

1

R7C4

2

1

R7D4

1

TP7D1

2

1

R7D1

2

1

R7C3

2

1

R4N4

1

TP4N1

2

1

R4N2

2

1

R4N3

2

1

R4N6

2

1

R4N5

2

1

R4N18

2

1

R6R10

2

1

R5P1

2

1

R6P13

M5

E2

C11
D11

BK9

CB9

CW12

CM39

D8
A9
E12
B12
A7
H4

DJ27

DF31

DV32

DW32

DT14

DR15

DT15

DF8

DU5

DB42
DB41

G1

DF4

CT39

K4
B9
D12
A12
B6

M7

U5E1

46C1 

19B8 

22D7  72A3  72B2 

22D2 

22D8 

30A8 

22C6  72A3  72B2 

22A3 

22A5 

22B3 

60A4 

60B3 

28A2 

22B8 

22D5 

30C2 

22D2 

22D2 

22C2 

22C2 

22D2 

22D2 

22C2 

22C2 

30A6 

22A3 

30A7 

29A5 

22B3 

22A8 

22A8 

22A5 

22B8 

22A5 

22B5 

22A8 

22C2 

22D2 

22D2 

22C2 

VCCSTG_TERM

VCCSTG_TERM

VCCSTG

V3P3_A

VCCSTG_TERM

VCCSTG_TERM

VCCSTG_TERM

VCCST_TERM

SOC

BMAP_REV=1.2

LPID6529

TGL_U_IP

21 OF 21

CH

1%

75K

0402LF

1%
CH

49.9

1/16W

0402LF

CH

1%

1/16W

0402LF

49.9

CH

1%

49.9

1/16W

0402LF

0402LF

499

CH

1%

1%

1K

0402LF

CH

1/16W

CH

5%

0

0201LF

0

0201LF CH

5%

5%
EMPTY

51

0402LF
1/16W

CH

51
5%

1/16W

0402LF

0 5%

CH

0201LF

0201LF

0 5%

CH

EMPTY

1/16W

51
5%

0402LF

5%

51

1/16W

EMPTY
0402LF

0 5%

CH

0201LF

1%
CH

1/16W

0402LF

100

5%

0

0201LF CH

0201LF

0

CH

5%

CH
0402LF

100
1%

1/16W

5%

0

CH

0201LF

0201LF

5%

0

CH

0402LF

5%

51

CH

1/16W

0402LF

5%

51

CH

1/16W

0201LF

0 5%

CH

0201LF CH

0 5%

EMPTY

51
5%

0402LF
1/16W

0402LF

EMPTY

1/16W

5%

51

1%
CH
0402LF

1K

1/16W

1/16W

5%

1K

0402LF

CH

EMPTY

5%

1K

0402LF
1/16W

CH

51
5%

1/16W

0402LF

1N5819HW

SMLF

DIO

D55839-001

5%

0402LF

CH

1/16W

100K

CH

0402LF

43 5%

JTAG_TDO

GPPC_H19

PECI

GPPC_B2_PROCHOT_N

H_PROCHOT_N

CPU_JTAG_TCK

PROCHOT_CPU_N
THRMTRIP_N

CPU_POPI_RCOMP
PCH_OPI_RCOMP

GPPC_H2

H_PROCHOT_N

CPU_JTAG_TMS

PCH_JTAG_TDO

PRDY_N

SIO_PECI

DBG_PMODE

CATERR_N

CPU_JTAG_TCK

PROCHOT_CPU_N

GPPC_F7

CPU_JTAG_TDO

CPU : JTAG/MISC

CPU_EAR_N

CPU_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TDI

JTAG_TDI

CPU_JTAG_TMS

PCH_JTAG_TMS

JTAG_TMS

PRDY_N

PREQ_N

GPPC_H0

JTAG_TCK

PCH_JTAG_TMS

GPPC_H1

GPPC_F9

GPPC_F10

PREQ_N

PCH_JTAG_TRST_N

PCH_JTAG_TCK

PCH_JTAG_TDI

PCH_JTAGX

CPU_JTAG_TDI

CPU_JTAG_TDO

CPU_JTAG_TRST_N

JTAG_TCK1

PCH_JTAG_TRST_N

JTAG_TRST_N

PCH_JTAGX

CPU_JTAG_TRST_N

PCH_JTAG_TCK

CAD NOTE:

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE: 

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

IN

OUT

OUT

OUT

BI

BI

OUT

OUT

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

BI

GPPC_F_10

GPPC_F_9_BOOTMPC

GPPC_F_7

EAR_N

PRDYB

PREQB

PCH_CPU_TRSTB

PCH_JTAG_TCK

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAGX

CPU_JTAG_TCK

CPU_JTAG_TDI

CPU_JTAG_TDO

CPU_JTAG_TMS

CPU_JTAG_TRSTB

GPPC_H_19_TIME_SYNC_0

GPPC_H_0

GPPC_H_1

GPPC_H_2

GPPC_E_3_CPU_GP_0

GPPC_E_7_CPU_GP_1

GPPC_B_3_CPU_GP_2

GPPC_B_4_CPU_GP_3

DBG_PMODE

PCH_OPIICCCTL

PCH_OPIICCOBS

PCH_OPIRCOMP

CPU_POPIRCOMP

THRMTRIPB

PROCHOTB

PECI

CATERRB

BI

OUT