The individual status registers are used to report different classes of instrument states or errors. The following status registers belong to the general model described in IEEE 488.2:
The STatus Byte (STB) gives a rough overview of the instrument status.
The IST flag combines the entire status information into a single bit that can be queried in a parallel poll.
The Event Status Register (ESR) indicates general instrument states.
The status registers below belong to the device-dependent SCPI register model:
The STATus:OPERation register contains conditions which are part of the instrument's normal operation.
The STATus:QUEStionable register indicates whether the data currently being acquired is of questionable quality.
The STATus:QUEStionable:LIMit<1|2> register indicates the result of the limit check.
The STATus:QUEStionable:INTegrity register monitors hardware failures of the analyzer.
The STatus Byte (STB) provides a rough overview of the instrument status by collecting the pieces of information of the lower registers. The STB represents the highest level within the SCPI hierarchy. A special feature is that bit 6 acts as the summary bit of the remaining bits of the status byte.
The STatus Byte (STB) is linked to the Service Request Enable (SRE) register on a bit-by-bit basis.
The STB corresponds to the EVENt part of an SCPI register, indicating the current instrument state.
The SRE corresponds to the ENABle part of an SCPI register.If a bit is set in the SRE and the associated bit in the STB changes from 0 to 1, a Service Request (SRQ) is generated on the GPIB bus.
Bit 6 of the SRE is ignored, because it corresponds to the summary bit of the STB.
The STB is read out using the command *STB? or a serial poll.
The SRE can be set using command *SRE and read using *SRE?.
The bits in the STB are defined as follows:
|
Bit No. |
Meaning |
|
3 |
QUEStionable status summary bit This bit is set if an EVENt bit is set in the QUEStionable register and the associated ENABle bit is set to 1. The bit indicates a questionable instrument status, which can be further pinned down by polling the QUEStionable register. |
|
5 |
ESB bit Sum bit of the event status register. It is set if one of the bits in the event status register is set and enabled in the event status enable register. Setting of this bit implies an error or an event which can be further pinned down by polling the event status register. |
In analogy to the Service Request (SRQ), the IST flag combines the entire status information in a single bit. It can be queried by means of a parallel poll.
The Parallel Poll Enable (PPE) register determines which bits of the STB contribute to the IST flag. The bits of the STB are ANDed with the corresponding bits of the PPE, with bit 6 being used as well in contrast to the SRE. The IST flag results from the ORing of all results.
The IST flag is queried using the command *IST?.
The Event Status Register (ESR) indicates general instrument states. It is linked to the Event Status Enable (ESE) register on a bit-by-bit basis.
The ESR corresponds to the CONDition part of an SCPI register, indicating the current instrument state.
The ESE corresponds to the ENABle part of an SCPI register. If a bit is set in the ESE and the associated bit in the ESR changes from 0 to 1, the ESB bit in the STatus Byte is set.
The Event Status Register (ESR) can be queried using ESR?.
The Event Status Enable (ESE) register can be set using the command *ESE and read using *ESE?.
The bits in the ESR are defined as follows:
|
Bit No. |
Meaning |
|
0 |
Operation Complete This bit is set on receipt of the command *OPC after all previous commands have been executed. |
|
2 |
Query Error This bit is set if either the controller wants to read data from the instrument without having sent a query, or if it does not fetch requested data and sends new instructions to the instrument instead. The cause is often a query which is faulty and hence cannot be executed. |
|
3 |
Device-Dependent Error This bit is set if a device-dependent error occurs. An error message with a number between -300 and -399 or a positive error number, which describes the error in greater detail, is entered into the error queue (see chapter Error Messages). |
|
4 |
Execution Error This bit is set if a received command is syntactically correct, but cannot be performed for other reasons. An error message with a number between -200 and -300, which describes the error in greater detail, is entered into the error queue (see chapter Error Messages). |
|
5 |
Command Error This bit is set if a command which is undefined or syntactically incorrect is received. An error message with a number between -100 and -200, which describes the error in greater detail, is entered into the error queue (see chapter Error Messages). |
|
6 |
User Request This bit is set when the instrument is switched over to manual control or when a user-defined softkey is used (SYSTem:USER:KEY...). |
|
7 |
Power On (supply voltage on) This bit is set when the instrument is switched on. |
The STATus:OPERation register contains conditions which are part of the instrument's normal operation.
The analyzer does not use the STATus:OPERation register.
The STATus:QUEStionable register indicates whether the acquired data is of questionable quality and monitors hardware failures of the analyzer. It can be queried using the commands STATus:QUEStionable:CONDition? or STATus:QUEStionable[:EVENt]?
The bits in the STATus:QUEStionable register are defined as follows:
|
Bit No. |
Meaning |
|
9 |
INTegrity register summary This bit is set if a bit is set in the STATus:QUEStionable:INTegrity register and the associated ENABle bit is set to 1. |
|
10 |
LIMit register summary This bit is set if a bit is set in the STATus:QUEStionable:LIMit1 register and the associated ENABle bit is set to 1. |
The STATus:QUEStionable:LIMit<1|2> registers indicate the result of the limit check. They can be queried using the commands STATus:QUEStionable:LIMit<1|2>:CONDition? or STATus:QUEStionable:LIMit<1|2>[:EVENt]? STATus:QUEStionable:LIMit1 is also the summary register of the lower-level STATus:QUEStionable:LIMit2 register.
The bits in the STATus:QUEStionable:LIMit1 register are defined as follows:
|
Bit No. |
Meaning |
|
0 |
LIMit2 register summary This bit is set if a bit is set in the STATus:QUEStionable:LIMit2 register and the associated ENABle bit is set to 1. |
|
1 |
Failed limit check for trace no. 1 This bit is set if any point on trace no. 1 fails the limit check. |
|
... |
... |
|
14 |
Failed limit check for trace no. 14 This bit is set if any point on trace no. 14 fails the limit check. |
The bits in the STATus:QUEStionable:LIMit2 register are defined as follows:
|
Bit No. |
Meaning |
|
0 |
Not used |
|
1 |
Failed limit check for trace no. 15 This bit is set if any point on trace no. 15 fails the limit check. |
|
2 |
Failed limit check for trace no. 16 This bit is set if any point on trace no. 16 fails the limit check. |
The traces numbers 1 to 16 are assigned as follows:
Traces assigned to channels with smaller channel numbers have smaller trace numbers.
Within a channel, the order of traces reflects their creation time: The oldest trace has the smallest, the newest trace has the largest trace number. This is equivalent to the order of traces in the response string of the CALCulate<Ch>:PARameter:CATalog? query.
The number of traces monitored cannot exceed 16. If a setup contains more traces, the newest traces are not monitored.
The STATus:QUEStionable:INTegrity register monitors hardware failures of the analyzer. It can be queried using the commands STATus:QUEStionable:INTegrity:CONDition? or STATus:QUEStionable:INTegrity[:EVENt]? STATus:QUEStionable:INTegrity is also the summary register of the lower-level STATus:QUEStionable:INTegrity:HARDware register.
Refer to the Error
Messages
section for a detailed description of hardware errors including
possible remedies.
The bits in the STATus:QUEStionable:INTegrity register are defined as follows:
|
Bit No. |
Meaning |
|
2 |
HARDware register summary This bit is set if a bit is set in the STATus:QUEStionable:INTegrity:HARDware register and the associated ENABle bit is set to 1. |
The STATus:QUEStionable:INTegrity:HARDware register can be queried using the commands STATus:QUEStionable:INTegrity:HARDware:CONDition? or STATus:QUEStionable:INTegrity:HARDware[:EVENt]?
The bits in the STATus:QUEStionable:INTegrity:HARDware register are defined as follows:
|
Bit No. |
Meaning |
|
0 |
Not used |
|
1 |
Reference frequency lock failure With external reference signal (System – External Reference active) or option ZVAB-B4 (oven quartz), the reference oscillator is phase locked to a 10 MHz signal. This bit is set if this phase locked loop (PLL) fails. For external reference: check frequency and level of the supplied reference signal. |
|
2 |
Output power unleveled This bit is set if the level control at one of the ports is unsettled or unstable, possibly due to an external disturbing signal. Change generator level at the port; check external components. |
|
3 |
Receiver overload protection tripped This bit is set if the analyzer detects an excessive input level at one of the ports. If this condition persists, all internal and external generators are switched off. Reduce RF input level at the port. Check amplifiers in the external test setup, then switch on the internal source using OUTPut ON. |
|
... |
Not used |
|
7 |
Instrument temperature is too high This bit is set if the analyzer detects that the instrument temperature is too high. Reduce ambient temperature, keep ventilation holes of the casing unobstructed. |
|
8 |
Oven cold This bit is set if the oven for the optional oven quartz (OCXO, option ZVAB-B4) is not at its operating temperature. Wait until the oven has been heated up. |
|
9 |
Unstable level control This bit is set if the analyzer detects an excessive source level at one of the ports. The signal is turned off and the sweep halted. Check signal path for the received wave, especially check external components. Then restart the sweep (INITiate<Ch>[:IMMediate]). |
|
10 |
Problem concerning external generator This bit is set if an external generator has been configured but cannot be controlled or provides error messages. Check whether the generator is properly connected and switched on. Check the GPIB address; exclude address conflicts when using several external generators or other equipment. |
|
11 |
Problem concerning external power meter This bit is set if an external power meter has been configured but cannot be controlled or provides error messages. Check whether the power meter is properly connected and switched on. Check the GPIB address; exclude address conflicts when using several external power meters or other equipment. |
|
12 |
Time grid too close This bit is set if the sweep points for a time sweep are too close, so that the analyzer cannot process the measurement data until the next sweep point starts. Increase stop time, reduce no. of points, increase IF bandwidth. If possible reduce number of partial measurements, e.g. by restricting the number of ports measured. |
|
13 |
Overload at DC MEAS This bit is set if the input voltage at one of the DC input connectors on the rear panel is too high. Reduce input voltage. |
|
14 |
Power settings exceed hardware limits This bit is set if the source power at one of the test ports is too high or too low. Reduce or increase the source power. |
|
15 |
Detector meas time has been internally limited This bit is set if the selected measurement time for a detector (observation time) is too long. If desired, reduce the measurement time or select a smaller IF bandwidth. |
