BACKGROUND
The invention relates to a linear regulator and, in particular, to a linear regulator providing a selectable output voltage.
FIG. 1 shows a conventional linear regulator commonly used by those skilled in the art. The bandgap reference circuit provides a stable voltage V.sub.bg. Noise of the voltage V.sub.bg is filtered out by a low pass filter typically comprising an on-chip resistor R.sub.bg and an off-chip capacitor C.sub.bp. The filtered signal V.sub.ref is sent to a first input terminal of an error amplifier. In the example shown in FIG. 1, the error amplifier is an operational amplifier and the first input terminal is the negative input of the operational amplifier. A second input, which is the positive input, of the operation amplifier is connected to a first node. A PMOS pass transistor M.sub.A is controlled by an output of the error amplifier. As shown in FIG. 1, a drain of the pass transistor M.sub.A is treated as the output terminal of the linear regulator. In order to guarantee the output stability of the linear regulator, a large external capacitor C.sub.OUT is typically connected to the output terminal. A first feedback resistor R.sub.1 is connected between the drain of the pass transistor M.sub.A and the first node. A second feedback resistor R.sub.2 is connected between the first node and the ground. Based on the virtual short between the input terminals of the error amplifier, an output voltage V.sub.OUT of the regulator can be adjusted by the ratio of the feedback resistors R.sub.1 and R.sub.2. As is known in the art, the output voltage V.sub.OUT is determined according to the voltage signal V.sub.ref, the first and second feedback resistors R.sub.1 and R.sub.2, and is obtained by
.times. ##EQU00001##
For some applications, multiple regulator output voltages are needed. FIG. 2 shows a conventional linear regulator which provides multiple output voltages. As shown in FIG. 2, a bandgap reference circuit is shared by two error amplifiers to reduce the required chip area. The external capacitor C.sub.bp is also typically shared such that the number of pins and external components can be minimized. Two sets of error amplifiers (error amplifiers A and B) and pass transistors (M.sub.A and M.sub.B) are used and different feedback resistor ratios are provided to generate different output voltages. According to FIG. 2, the output voltages V.sub.OUTA and V.sub.OUTB can be found to be
.times. ##EQU00002## and
.times. ##EQU00003## respectively.
A linear regulator with a selectable output voltage is disclosed in U.S. Pat. No. 6,593,607 by Nicolas Marty et. al. As shown in FIG. 3, the linear regulator comprises a power MOS transistor 2 controlled by a differential amplifier 5. The differential amplifier 5 has an input terminal 8 receiving, via a circuit of resistors R.sub.1, R.sub.2, R.sub.3 switchable by means of MOS control transistors 12 and 14, a voltage proportional to the output voltage V.sub.OUT provided by the regulator. The regulator further includes at least two circuits for generating the control signals CTRL1 and CTRL2 for controlling the respective gates of the control transistors 12 and 14. When the control signals CTRL1 and CTRL2 are respectively at a low and high state, the output voltage V.sub.OUT equals
.times. ##EQU00004## To the contrary, when the signals CTRL1 and CTRL2 are respectively at a high and low state, the output voltage V.sub.OUT equals
.times. ##EQU00005## Theoretically, the desired values of the output voltage V.sub.OUT can always be achieved by arbitrarily setting the values of the resistors R.sub.1, R.sub.2, and R.sub.3. However, in practical, the values of these resistors cannot be arbitrary ones in consideration of layout matching as well as the output voltage accuracy. This fact makes the choice of the resistors become difficult, especially when the desired levels of the output voltage is more than two, in a design based on the one shown in FIG. 3.
SUMMARY
An embodiment of a switchable linear regulator for providing a selectable output voltage comprises a constant voltage source, a differential amplifier, a pass element transistor, a first resistor, a plurality of second resistors and a plurality of switches. The differential amplifier has a first input terminal coupled to the constant voltage source and a second input terminal connected to a first node. The pass element transistor has a first terminal controlled by the differential amplifier and a second terminal connected to a supply voltage. The first resistor is connected between the pass transistor and the first node. Each second resistor comprises one end connected to the first node. Each switch is coupled between the other end of a corresponding second resistor and a fixed voltage.
DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a conventional liner regulator commonly used by those skilled in the art.
FIG. 2 shows a conventional linear regulator which provides multiple output voltages.
FIG. 3 shows a linear regulator with a selectable output voltage disclosed in U.S. Pat. No. 6,593,607 by Nicolas Marty et. al.
FIG. 4 shows a circuit diagram of a switchable linear regulator according to an embodiment of the invention.
FIG. 5 shows a circuit diagram of a switchable linear regulator derived from that shown in FIG. 4.
FIG. 6 shows a circuit diagram of a linear regulator with a selectable output voltage derived from U.S. Pat. No. 6,593,607.
FIG. 7 shows a circuit diagram of a switchable linear regulator according to an embodiment of the invention.
DETAILED DESCRIPTION
FIG. 4 shows a circuit diagram of a switchable linear regulator according to an embodiment of the invention. The switchable linear regulator comprises a constant voltage source CVS, a differential amplifier DA, a pass transistor M.sub.A, a first resistor R.sub.b, two second resistors R.sub.1, R.sub.2, a first switch SW.sub.1, and a second switch SW.sub.2. The constant voltage source CVS provides a constant voltage V.sub.ref to a first input terminal of the differential amplifier DA. A second input terminal of the differential amplifier DA is coupled to a first node A. A first terminal of the pass transistor M.sub.A is controlled by the differential amplifier DA. A second and third terminal of the pass transistor M.sub.A is respectively coupled to a supply voltage V.sub.IN and the second node B. The output terminal V.sub.OUT is coupled to the second node B. Preferably, the pass transistor M.sub.A is a PMOS transistor and the first and second input terminals of the differential amplifier DA are respectively the negative and positive input. A first resistor R.sub.b is connected between the first node A and second node B. Each of the second resistors R.sub.1, R.sub.2 has one end connected to the first node A. The first switch SW.sub.1 is coupled between the other end of the second resistor R.sub.1 and a fixed voltage, and is controlled by a first control signal S1. The second switch SW.sub.2 is coupled between the other end of the second resistor R.sub.2 and the fixed voltage, and is controlled by a second control signal S2. Preferably, the fixed voltage is a ground.
More specifically, the constant voltage source CVS of the switchable linear regulator comprises a bandgap reference circuit BR coupled to the supply voltage V.sub.IN. Furthermore, the constant voltage source CVS may comprise a RC low pass filter connected between the first input terminal of the differential amplifier DA and the bandgap reference circuit BR. The bandgap reference circuit BR provides a stable voltage V.sub.bg. Noise of the voltage V.sub.bg is filtered out by a low pass filter comprising a resistor R.sub.bg and a capacitor C.sub.bp. The filtered signal V.sub.ref is a constant voltage and sent to the first input terminal of the differential amplifier DA.
Moreover, the switchable linear regulator may comprise a capacitor C.sub.OUT coupled between the output terminal and the fixed voltage. The capacitor C.sub.OUT improves stability of the output voltage V.sub.OUT of the switchable linear regulator.
FIG. 5 shows a circuit diagram of a switchable linear regulator derived from the one shown in FIG. 4. The switchable linear regulator further comprises an output switch unit OSU having an input and a plurality of outputs. The output switch unit OSU is controlled by the first and second control signals S1 and S2 for selectively connecting one of the plurality of outputs to the input such that the output terminal of the switchable linear regulator is further selectable according to the control signals S1 and S2. In the example shown in FIG. 5, the output switch unit OSU is employed to make the terminal V.sub.OUTA as the active output terminal of the switchable linear regulator when the first control signal S1 triggers the first switch SW1 to be ON state; and make the terminal V.sub.OUTB as the active output terminal of the switchable linear regulator when the second control signal S2 triggers the second switch SW2 to be ON state. In such an example, the output switch unit OSU contains a first output switch SW'.sub.1 and a second output switch SW'.sub.2 both connected to the input, i.e. the second node B. The first output switch SW'.sub.1 is connected between the second node B and the output terminal V.sub.OUTA, and is controlled by the first control signal S1. The first control signal S1 that triggers the first switch SW1 to be ON state will also trigger the first output switch SW'.sub.1 to be ON state. The second output switch SW'.sub.2 is connected between the second node B and the output terminal V.sub.OUTB. The second control signal S2 that triggers the second switch SW2 to be ON state will also trigger the second output switch SW'.sub.2 to be ON state. Compared with the linear regulator shown in FIG. 2, one differential amplifier and one pass transistor are eliminated in the circuitry of the switchable linear regulator. Thus, the chip area can be reduced and the number of pins and external components is also reduced. When the first control signals S1 triggers the switches SW.sub.1 and SW'.sub.1 to be ON state and the second control signal S2 triggers the switches SW2 and SW'.sub.2 to be OFF state, V.sub.OUT equals
.times. ##EQU00006## and the active output terminal of the switchable linear regulator is V.sub.OUTA. On the contrary, when the first control signals S1 triggers the switches SW.sub.1 and SW'.sub.1 to be OFF state and the second control signal S2 triggers the switches SW2 and SW'.sub.2 to be ON state, V.sub.OUT equals
.times. ##EQU00007## and the active output terminal of the switchable linear regulator is V.sub.OUTB. In this embodiment, the switchable linear regulator provides a selectable output voltage as well as a selectable output terminal. Meanwhile, the chip area and the number of pins and external components are minimized.
In order to provide an accurate output voltage, matching of the feedback resistors is typically a major concern in a regulator design. Utilization of unit cells to implement feedback resistors and inter-digitized layout improves matching thereof. In other words, the selected feedback resistor values need to have a reasonable common divisor for convenience of layout. Take a linear regulator with two selectable output voltages as an example. In FIG. 3, the design equations are respectively
.times. ##EQU00008## and
.times. ##EQU00009## Both equations are functions of the same three design variables and closely related to one another. In FIG. 4, however, the design equations are respectively
.times. ##EQU00010## and
.times. ##EQU00011## As long as the value of resistor R.sub.b is chosen, R.sub.1 and R.sub.2 can be determined according to the output voltage V.sub.OUT and the constant voltage V.sub.ref. Thus, the regulator design is simplified.
However, when more selectable output voltages are required, the design of the invention is much simplified as compared with the conventional regulators. If three output voltages are required, the regulator in FIG. 3 is expanded to the one shown in FIG. 6. The design equations are shown as follows,
.fwdarw..times. ##EQU00012## .fwdarw..times. ##EQU00012.2## .fwdarw..times. ##EQU00012.3##
When the same output voltages are implemented in the invention, the circuit diagram is shown in FIG. 7. The design equations are shown as follows,
.fwdarw..times..fwdarw..times..fwdarw..times. ##EQU00013##
It is clear that the design equations of the invention are simpler than the conventional regulators. Although only one case is given as an example to demonstrate the advantage of the invention. Its applicability to other circumstances is readily apparent. It is assumed that V.sub.ref=1.2 V and the three output voltages are respectively 2.8 V, 2 V and 1.4 V. According to the invention, it is very easy to obtain a suitable combination of the resistors R.sub.b=40 k.OMEGA., R.sub.1=30 k.OMEGA., R.sub.2=60 k.OMEGA. and R.sub.3=240 k.OMEGA..
A unit cell of 10 k.OMEGA. or 20 k.OMEGA. can be used to realize the resistor layouts. To the contrary, the design of the conventional regulator is more complicated while practically implementing it. From the design equations, it is found that 5R.sub.3=2R.sub.4, 9R.sub.1=5R.sub.2 and 3R.sub.1=R.sub.4. Thus, a solution of R.sub.1=30 .OMEGA., R.sub.2=54 k.OMEGA., R.sub.3=4 k.OMEGA. and R.sub.4=10 k.OMEGA. can be derived. Apparently, it is more difficult to find a suitable common divisor as a layout unit cell.
While the invention has been described by way of examples and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and the advantages would be apparent compared to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications. |
